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MD1730 Datasheet(PDF) 22 Page - Microchip Technology |
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MD1730 Datasheet(HTML) 22 Page - Microchip Technology |
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22 / 34 page  MD1730 DS20005586B-page 22 2016 Microchip Technology Inc. FIGURE 4-7: MD1730 Working with Two HV7321 Pulsers Pinout and Package. 4.7 CW Transmission Clock The input clock of the MD1730, used for CW transmission, can be connected either differentially or single-ended. Figure 4-8 shows the LVDS differential implementation for the transmission clock. Here the CLKP and the CLKN pins are directly driven by a LVDS clock buffer. It is highly recommended that a multiple-output LVDS clock buffer IC is used, such as the SY89832U, and that a 100Ω termination resistor is placed very close to the CLKP and CLKN pins. For successful transmission of the LVDS signal over differential traces, the following guidelines should be followed while laying out the PCB board: • To ensure minimal reflections and to maintain the receiver’s common-mode noise rejection, keep the differential traces as short as possible between the clock buffer IC and the CLKP/CLKN pins of the MD1730. • To reduce skew, the electrical lengths between differential LVDS traces should be identical. The arrival of one differential signal before the other will create a phase difference between the signal pairs, which would create clock skew and impair the system performance. • Minimize the number of vias or other discontinuities in the signal path. To avoid discontinuities, arcs or 45-degree traces are recommended instead of 90-degree turns. • Any parasitic loading, such as capacitance, must be present in equal amounts on each differential line. Figure 4-9 illustrates the two cases for the MD1730 used in a single-ended configuration. In these cases, one of the clock input pins, CLKP or CLKN, is connected to the VLL/2 voltage level and bypassed to ground with a 0.1 uF bypass capacitor. Each bypass capacitor must be placed very close to the MD1730. The other clock input pin connects to the main clock line. The PCB traces on the clock line must be designed for a 50Ω impedance with respect to the PCB ground place. Also, the clock pin must be terminated with a small 50Ω SMT resistor. Generally, the LVCMOS input configuration provides better CW phase noise performance due to its higher amplitude swing as compared to the LVDS configuration. However, if the user needs a very high frequency clock transmission, such as 160 MHz- 240 MHz range for a higher phase delay resolution, then LVDS should be used because it provides a better PCB clock trace distribution. CPF1 VPP1 TX3 RXO3 RGN D RXO1 TX1 CPOS CNEG TX2 RXO2 RGN D RXO3 TX3 VPP1 CPF1 CWIN0 SEL1 NEG1 POS1 CWIN1 SEL2 NEG2 POS2 CWIN2 SEL3 REN VLL GND CLK PWS OEN CPF1 VPP1 TX3 RXO3 RGN D RXO1 TX1 CPOS CNEG TX2 RXO2 RGN D RXO3 TX3 VPP1 CPF1 CWIN0 SEL1 NEG1 POS1 CWIN1 SEL2 NEG2 POS2 CWIN2 SEL3 REN VLL GND CLK PWS OEN 9x9mm QFN-64 9x9mm QFN-64 To Probe & Rx LNA CW0 CW2 CW3 CW4 CW5 CW6 EN VDD CLK CLK CS SCK SDI 6x6mm QFN-36 CW1 CW7 VGN VLL GND |
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