MD1730 datasheet(20/34 Pages) MICROCHIP

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MD1730

DS20005586B-page 20

 2016 Microchip Technology Inc.

FIGURE 4-5:

Clock Buffers CKB0/1 Output Timing Diagram.

4.6

MD1730 Working with Two HV7321

The diagrams shown in Figure 4-6 and Figure 4-7

illustrate the MD1730 driving two HV7321s.

When the HV7321 is operated in the specific mode,

CW MODE = 1, along with the MD1730, the following

steps should be taken to ensure the combination

settings work correctly:

Apply all power supply rails to both chips and set

HV7321’s OEN = REN = PWS = 1 along with

MD1730’s EN = 1 to enable both chips. Set all

other control logic pins to zero.

Adjust the VCW+ and VCW- power supplies to

the required peak-to-peak voltage levels for CW

output transmission. Please note that a higher

peak-to-peak transmission voltage will result in

the MD1730 dissipating more power. The power

dissipation on the MD1730 is proportional to the

square of the peak-to-peak voltage.

Assert HV7321’s MODE pin high.

Program the MD1730 with the desired CW

frequency divider and delay settings for CW

transmission.

10. To place a channel in receive mode, set the

corresponding pins SEL, NEG, POS = 011b on

the HV7321. To place a channel to CW Transmit

mode, set the corresponding pins SEL, NEG,

POS to any other combination other than 011b

on HV7321. This will put that channel of the

HV7321 high voltage Tx output in High Z mode,

but turn the channel’s CWSW on.

In the case user wants a channel not in High Z or CW

Transmit mode, then similarly, to set the channel of

HV7321 to High Z and also set the MD1730’s

corresponding bit in the HIZ register to 1.

11. Once the system is ready to perform CW

Doppler measurement, assert TXRW high to

start the CW transmission on the selected

channels.

CKB0

tdrb

tdfb

CLKP

(fCLK)

CKB1

CBE0

CBE1

trb

tcbe

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