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MD1730 Datasheet(PDF) 16 Page - Microchip Technology |
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MD1730 Datasheet(HTML) 16 Page - Microchip Technology |
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16 / 34 page ![]() MD1730 DS20005586B-page 16 2016 Microchip Technology Inc. REGISTER 4-2: SPI REGISTER ADDRESS AND CONTROL BITS 4.4 Serial Peripheral Interface (SPI) The MD1730’s SPI is used to program the phase delay and frequency divider registers. The SPI supports writing at speed up to 200 MHz and the MSB is shifted in first. SPI interface supports two operating modes: daisy chain mode and broadcasting mode. When SPIB = 0, the MD1730 is in daisy chain mode. In this mode, it supports both read and write operations. When SPIB = 1 the chip enters the “Broadcasting” mode. In this mode, the SDI data shifts into the shift register as well as to the SDO output. In this mode, the user can write the same register of different daisy chained chips with the same value in a single write transaction. However, when SPIB = 1 the read operation is disabled. To verify the written data for each chip, the user can revert SPIB = 0 and perform a normal read operation. 4.4.1 SPI WRITE OPERATION EXAMPLES The following is a 1-byte writing example for the register at ADD = 0011b with the data D<7:0> = 01010101 when SPIB = TXRW = 0. 1. The Write operation starts with setting CSN to low. 2. The SCK clock is used to shift in the following SDI data: W/R SPI Register ADD<3:0> Write or Read Data <7:0> D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 = Write 0 = Read MSB first. (See Section 4.3 and Section 4.4 ) 00 0 0 Channel 0 phase delay PHD0<7:0> 00 0 1 Channel 1 phase delay PHD1<7:0> 00 1 0 Channel 2 phase delay PHD2<7:0> 00 1 1 Channel 3 phase delay PHD3<7:0> 01 0 0 Channel 4 phase delay PHD4<7:0> 01 0 1 Channel 5 phase delay PHD5<7:0> 01 1 0 Channel 6 phase delay PHD6<7:0> 01 1 1 Channel 7 phase delay PHD7<7:0> 10 0 0 HIZ7 HIZ6 HIZ5 HIZ4 HIZ3 HIZ2 HIZ1 HIZ0 10 0 1 CW frequency divisor number CWFD<7:0> Note: Power-On or EN = 0 sets all the registers to 0. TABLE 4-1: PHD<7:0> PHASE DELAY TIME REGISTER DESCRIPTION PHD<7:0> Delay Time to Start Transmitting 00000000 0/fCLK (Power-on default) 00000001 1/fCLK 00000010 2/fCLK ......... ........ 11111110 254/fCLK 11111111 255/fCLK TABLE 4-2: CWFD<7:0> CW FREQUENCY DIVIDER REGISTER DESCRIPTION CWFD[7:0] Transmit CW Frequency fCW 00000000 fCLK/512 (Power-on default) 00000001 fCLK/2 00000010 fCLK/4 00000011 fCLK/6 ......... ........ 11111110 fCLK/508 11111111 fCLK/510 Note: The selected CW frequency is same for all the CW0~7 outputs: fCW = fCLK/2*CWFD. The CW frequency applies to all channels. |
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