LAN9115 datasheet(24/114 Pages) MICROCHIP

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LAN9115

DS00002269A-page 24

 2005-2016 Microchip Technology Inc.

3.8

General Purpose Timer (GP Timer)

The General Purpose Timer is a programmable block that can be used to generate periodic host interrupts. The reso-

lution of this timer is 100uS.

The GP Timer loads the GPT_CNT Register with the value in the GPT_LOAD field and begins counting down when the

TIMER_EN bit is set to a ‘1.’ On a reset, or when the TIMER_EN bit changes from set ‘1’ to cleared ‘0,’ the GPT_CNT

field is initialized to FFFFh. The GPT_CNT register is also initialized to FFFFh on a reset. Software can write the pre-

load value into the GPT_LOAD field at any time; e.g., before or after the TIMER_EN bit is asserted. The GPT Enable

bit TIMER_EN is located in the GPT_CFG register.

Once enabled, the GPT counts down either until it reaches 0000h or until a new pre-load value is written to the GPT_-

LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT interrupt status bit and the IRQ signal if the

GPT_INT_EN bit is set, and continues counting. The GPT interrupt status bit is in the INT_STS Register. The GPT_INT

hardware interrupt can only be set if the GPT_INT_EN bit is set. GPT_INT is a sticky bit (R/WC); i.e., once the GPT_INT

bit is set, it can only be cleared by writing a ‘1’ to the bit.

3.9

EEPROM Interface

LAN9115 can optionally load its MAC address from an external serial EEPROM. If a properly configured EEPROM is

detected by LAN9115 at power-up, hard reset or soft reset, the ADDRH and ADDRL registers will be loaded with the

contents of the EEPROM. If a properly configured EEPROM is not detected, it is the responsibility of the host LAN Driver

to set the IEEE addresses.

The LAN9115 EEPROM controller also allows the host system to read, write and erase the contents of the Serial

EEPROM. The EEPROM controller supports most “93C46” type EEPROMs configured for 128 x 8-bit operation.

3.9.1

MAC ADDRESS AUTO-LOAD

On power-up, hard reset or soft reset, the EEPROM controller attempts to read the first byte of data from the EEPROM

(address 00h). If the value A5h is read from the first address, then the EEPROM controller will assume that an external

Serial EEPROM is present. The EEPROM controller will then access the next EEPROM byte and send it to the MAC

Address register byte 0 (ADDRL[7:0]). This process will be repeated for the next five bytes of the MAC Address, thus

fully programming the 48-bit MAC address. Once all six bytes have been programmed, the “MAC Address Loaded” bit

is set in the E2P_CMD register. A detailed explanation of the EEPROM byte ordering with respect to the MAC address

is given in Section 5.4.3, "ADDRL—MAC Address Low Register," on page 82.

If an 0xA5h is not read from the first address, the EEPROM controller will end initialization. It is then the responsibility

of the host LAN driver software to set the IEEE address by writing to the MAC’s ADDRH and ADDRL registers.

The host can initiate a reload of the MAC address from the EEPROM by issuing the RELOAD command via the E2P

command (E2P_CMD) register. If the first byte read from the EEPROM is not A5h, it is assumed that the EEPROM is

not present, or not programmed, and the MAC address reload will fail. The “MAC Address Loaded” bit indicates a suc-

cessful reload of the MAC address.

3.9.2

EEPROM HOST OPERATIONS

After the EEPROM controller has finished reading (or attempting to read) the MAC after power-on, hard reset or soft

reset, the host is free to perform other EEPROM operations. EEPROM operations are performed using the E2P_CMD

and E2P data (E2P_DATA) registers. Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 77 provides

an explanation of the supported EEPROM operations.

If the EEPROM operation is the “write location” (WRITE) or “write all” (WRAL) commands, the host must first write the

desired data into the E2P_DATA register. The host must then issue the WRITE or WRAL command using the E2P_CMD

must also be set to the desired location. The command is executed when the host sets the EPC_BSY bit high. The com-

pletion of the operation is indicated when the EPC_BSY bit is cleared.

If the EEPROM operation is the “read location” (READ) operation, the host must issue the READ command using the

E2P_CMD with the EPC_ADDR set to the desired location. The command is executed when the host sets the EPC_BSY

bit high. The completion of the operation is indicated when the EPC_BSY bit is cleared, at which time the data from the

EEPROM may be read from the E2P_DATA register.

Other EEPROM operations are performed by writing the appropriate command to the EPC_CMD register. The com-

mand is executed when the host sets the EPC_BSY bit high. The completion of the operation is indicated when the

EPC_BSY bit is cleared. In all cases the host must wait for EPC_BSY to clear before modifying the E2P_CMD register.

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