LAN9115 datasheet(72/114 Pages) MICROCHIP

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LAN9115

DS00002269A-page 72

 2005-2016 Microchip Technology Inc.

5.3.14

GPIO_CFG—GENERAL PURPOSE IO CONFIGURATION REGISTER

This register configures the GPIO and LED functions.

PME Enable (PME_EN). When set, this bit enables the external PME signal.

This bit does not affect the PME interrupt (PME_INT).

R/W

Device Ready (READY). When set, this bit indicates that LAN9115 is ready

to be accessed. This register can be read when LAN9115 is in any power

management mode. Upon waking from any power management mode,

including power-up, the host processor can interrogate this field as an

indication when LAN9115 has stabilized and is fully alive. Reads and writes of

any other address are invalid until this bit is set.

Note:

With the exception of HW_CFG and PMT_CTRL, read access to

any internal resources is forbidden while the READY bit is cleared.

Offset:

88h

Size:

32 bits

Bits

Description

Type

Default

Reserved

30:28

LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated pin as an LED output.

When cleared low, the pin functions as a GPIO signal.

LED1/GPIO0 – bit 28

LED2/GPIO1 – bit 29

LED3/GPIO2 – bit 30

R/W

000

Reserved

26:24

GPIO Interrupt Polarity 0-2 (GPIO_INT_POL). When set high, a high logic

level on the corresponding GPIO pin will set the corresponding INT_STS

will set the corresponding INT_STS register bit.

GPIO Interrupts must also be enabled in GPIOx_INT_EN in the INT_EN

GPIO0 – bit 24

GPIO1 – bit 25

GPIO2 – bit 26

Note:

GPIO inputs must be active for greater than 40nS to be recognized

as interrupt inputs.

R/W

000

Reserved

22:20

EEPROM Enable (EEPR_EN). The value of this field determines the function

of the external EEDIO and EECLK:

Please refer to Table 5-4 for the EEPROM Enable bit function definitions.

Note:

The host must not change the function of the EEDIO and EECLK

pins when an EEPROM read or write cycle is in progress. Do not use

reserved settings.

Note:

Regardless of whether the internal or external PHY is selected,

RX_DV, TX_CLK and RX_CLK reflect the signals on the internal

PHY and the MAC always drives TX_EN.

R/W

000

Reserved

18:16

GPIO Buffer Type 0-2 (GPIOBUFn). When set, the output buffer for the

corresponding GPIO signal is configured as a push/pull driver. When cleared,

the corresponding GPIO set configured as an open-drain driver.

GPIO0 – bit 16

GPIO1 – bit 17

GPIO2 – bit 18

R/W

000

15:11

Reserved

Bits

Description

Type

Default

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