LAN9211 datasheet(109/147 Pages) SMSC

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9211

109

Revision 2.9 (03-01-12)

DATASHEET

5.4.3

ADDRL—MAC Address Low Register

The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The

contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM

Controller if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0])

is loaded from address 0x01 of the EEPROM. The most significant byte of this register is loaded from

address 0x04 of the EEPROM. Please refer to Section 4.6 for more information on the EEPROM.

Table 5.7 below illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the

reception of the Ethernet physical address. Also shown is the correlation between the EEPROM

addresses and ADDRL and ADDRH registers.

As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and

ADDRH registers would be programmed as shown in Figure 5.2. The values required to automatically

load this configuration from the EEPROM are also shown.

Figure 5.2 Example ADDRL, ADDRH and EEPROM Setup

Offset:

Attribute:

R/W

Default Value:

FFFFFFFFh

Size:

32 bits

BITS

DESCRIPTION

31-0

Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the

LAN9211 device. The content of this field is undefined until loaded from the EEPROM at power-on.

The host can update the contents of this field after the initialization process has completed.

Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering

EEPROM ADDRESS

ADDRN

ORDER OF RECEPTION ON

ETHERNET

0x01

ADDRL[7:0]

1st

0x02

ADDRL[15:8]

2nd

0x03

ADDRL[23:16]

3rd

0x04

ADDRL[31:24]

4th

0x05

ADDRH[7:0]

5th

0x06

ADDRH[15:8]

6th

0x12

0x34

0x56

0x78

ADDRL

0x9A

0xBC

ADDRH

0xA5

0x12

0x34

0x56

0x78

0x9A

0xBC

0x00

0x01

0x02

0x03

0x04

0x05

0x06

EEPROM

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