LAN9211 datasheet(108/147 Pages) SMSC

108 / 147 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

108

SMSC LAN9211

DATASHEET

5.4.2

ADDRH—MAC Address High Register

The MAC Address High register contains the upper 16-bits of the physical address of the MAC. The

contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM

Controller if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0])

is loaded from address 0x05 of the EEPROM. The second byte (bits [15:8]) is loaded from address

0x06 of the EEPROM. Please refer to Section 4.6 for more information on the EEPROM. Section 5.4.3

details the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the

Ethernet physical address.

Offset:

Attribute:

R/W

Default Value:

0000FFFFh

Size:

32 bits

BITS

DESCRIPTION

31-16

Reserved

15-0

Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of

the LAN9211 device. The content of this field is undefined until loaded from the EEPROM at power-

on. The host can update the contents of this field after the initialization process has completed.

LAN9211 Datasheet(PDF) 108 Page - SMSC Corporation