LAN9211 datasheet(134/147 Pages) SMSC

134 / 147 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

134

SMSC LAN9211

DATASHEET

6.7

TX Data FIFO Direct PIO Writes

In this mode the upper address inputs are not decoded, and any write to the LAN9211 will write the

TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is

normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is

useful when the host processor must increment its address when accessing the LAN9211. Timing is

identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address

lines.

Note: The “Data Bus” width is 16 bits.

Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The

cycle ends when either or both nCS and nWR are deasserted. They may be asserted and

deasserted in any order.

Figure 6.6 TX Data FIFO Direct PIO Write Timing

Table 6.8 TX Data FIFO Direct PIO Write Timing

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tcycle

Write Cycle Time

tcsl

nCS, nWR Assertion Time

tcsh

nCS, nWR Deassertion Time

tasu

Address, FIFO_SEL Setup to nCS, nWR Assertion

tah

Address, FIFO_SEL Hold Time

tdsu

Data Setup to nCS, nWR Deassertion

tdh

Data Hold Time

Data Bus

nCS, nWR

FIFO_SEL

A[2:1]

LAN9211 Datasheet(PDF) 134 Page - SMSC Corporation

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