LAN9211 datasheet(132/147 Pages) SMSC

132 / 147 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

132

SMSC LAN9211

DATASHEET

6.5

RX Data FIFO Direct PIO Burst Reads

In this mode the upper address inputs are not decoded, and any burst read of the LAN9211 will read

the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This

is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode

is useful when the host processor must increment its address when accessing the LAN9211. Timing

is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the

address lines.

In this mode, performance is improved by allowing an unlimited number of back-to-back read cycles.

RX Data FIFO Direct PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable

(nRD). When either or both of these control signals go high, they must remain high for the period

specified.

Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.

Note: The “Data Bus” width is 16 bits.

Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.

The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and

deasserted in any order.

Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing

Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tcsh

nCS, nRD Deassertion Time

tcsdv

nCS, nRD Valid to Data Valid

tacyc

Address Cycle Time

tasu

Address, FIFO_SEL Setup to nCS, nRD Valid

tadv

Address Stable to Data Valid

tah

Address, FIFO_SEL Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

tdoh

Data Output Hold Time

Data Bus

nCS, nRD

FIFO_SEL

A[2:1]

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