LAN9211 datasheet(128/147 Pages) SMSC

128 / 147 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

128

SMSC LAN9211

DATASHEET

6.1.2

Special Restrictions on Back-to-Back Read Cycles

There are also restrictions on specific back-to-back read operations. These restrictions concern

reading specific registers after reading resources that have side effects. In many cases there is a delay

between reading the LAN9211, and the subsequent indication of the expected change in the control

In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have

been established. These periods are specified in Table 6.2, "Read After Read Timing Rules". The host

processor is required to wait the specified period of time between read operations of specific

combinations of resources. The wait period is dependant upon the combination of registers being read.

Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the

minimum wait time restriction is met. Table 6.2 also shows the number of dummy reads that are

required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on

the minimum timing for Tcycle (45ns). For microprocessors with slower busses the number of reads

may be reduced as long as the total time is equal to, or greater than the time specified in the table.

Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.

Table 6.2 Read After Read Timing Rules

AFTER

READING...

WAIT FOR THIS MANY

NS…

OR PERFORM THIS MANY

READS OF BYTE_TEST…

(ASSUMING Tcycle OF 45NS)

BEFORE READING...

RX Data FIFO

135

RX_FIFO_INF

RX Status FIFO

135

RX_FIFO_INF

TX Status FIFO

135

TX_FIFO_INF

RX_DROP

180

RX_DROP

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