| Electronic Components Datasheet Search |
|
DSP56156ROM Datasheet(PDF) 34 Page - Motorola, Inc |
|
|
|||||||||||||||||||||||||||||
DSP56156ROM Datasheet(HTML) 34 Page - Motorola, Inc |
|
34 / 76 page ![]() AC Electrical Characteristics and Timing 34 DSP56156 Data Sheet MOTOROLA Bus Arbitration Timing — Slave Mode (VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load) cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles WS = Number of Wait States for external X or P memory, Determined by BCR Register (WS = 0 to 31) WT = WS × cyc=2T × WS WX = Number of Wait States for external X memory, Determined by BCR Register (WS = 0 to 31) WP = Number of Wait States for external P memory, Determined by BCR Register (WS = 0 to 31) NOTES: 1. With no external access from the DSP56156 2. During external read or write access 3. During external read-modify-write access 4. During Stop mode — external bus is released and BG is always low 5. During Wait mode 6. With external accesses pending by the DSP56156 7. Slave mode, when bus is still busy after bus request has been deasserted Table 17 Slave Mode Num Characteristics 40/50/60 MHz Unit Min Max 70 BR Input to CLKO low setup time 0 1 ns 71 Delay from BR Input Assertion to (See Note 1) BG Output Assertion (See Note 2) (See Note 3) (See Note 4) (See Note 5) 5T+1.9 3T+1.9 5T+1.9 NA T+1.9 9T+4.2 6T+WT+4.2 26T+4T x WX +2T x WP+4.2 NA 3T+4.2 ns 72 CLKO high to BG Output Assertion 1.9 5.2 ns 73 BG Output Deassertion Duration (See Note 1) (See Note 5) (See Note 6) 5T-0.5 2T-0.5 3T-0.5 — — — ns 74 CLKO High to Control Bus High Impedance 2.7 6.5 ns 75 CLKO High to BB Output Deassertion 3.2 7.8 ns 76 CLKO High to BB Input 3.3 8.1 ns 77 BR Input Deassertion to (See Note 1) BG Output Deassertion (See Note 5) (See Note 7) 4T+2.5 3T+3.2 3T+3.2 9T+6.4 8T+7.8 8T+8.0 ns 78 CLKO Low to BG Deassertion (See Note 1) CLKO High to BG Deassertion (See Note 5) CLKO High to BG Deassertion (See Note 7) 2.5 3.2 3.2 6.4 7.8 8.0 ns 79 CLKO High to BB Output Active 1.3 3.6 ns 80 CLKO High to BB Output Assertion 2.3 5 ns 81 CLKO High to Address and Control Bus Active 1 3 ns 82 CLKO High to Address and Control Bus Valid 2 4.4 ns Bus Arbitration Timing — Slave Mode Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |