DSP56156ROM datasheet(44/76 Pages) MOTOROLA

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

Synchronous Serial Interfaces (SSI) Timing

(VCC = 5.0 V dc ± 10%, TJ = -40° to + 125°C, CL = 50 pF + 1 TTL Load)

T= ICYC / 4

SCK = Serial Clock Pin

FST (Transmit Frame Sync)

= SCx0 Pin

FSR (Receive Frame Sync)

= SCx1 Pin

i ck = Internal Clock

x ck = External Clock

i ck a = Internal Clock, Asynchronous Mode (Asynchronous

implies that FSR and FST are two different frame syncs)

i ck s = Internal Clock, Synchronous Mode (Synchronous implies

that only one frame sync FS is used)

bl = bit length

wl = word length

NOTE: All the timings for the SSI are given for a non-inverted serial clock polarity (SCKP=0 in CRB) and a non-

inverted frame sync (FSI=0 in CRB). If the polarity of the clock and/or the frame sync have been inverted,

all the timings remain valid by inverting the clock signal SCK and/or the frame sync FSR/FST in the tables

and in the figures.

Table 20 Synchronous Serial Interfaces Timing

Num

Characteristic

40/50/60 MHz

Case

Unit

Min

Max

130

Clock Cycle (See Note)

100

——

131

Clock High Period

—

132

Clock Low Period

—

133

Output Clock Rise/Fall Time

—

134

SCK Rising Edge to FSR Out

(bl) High

—

x ck

i ck a

135

SCK Rising Edge to FSR Out

(bl) Low

—

x ck

i ck a

136

SCK Rising Edge to FSR Out

(wl) High

—

x ck

i ck a

137

SCK Rising Edge to FSR Out

(wl) Low

—

x ck

i ck a

138

Data In Setup Time before SCK

Falling Edge

—

x ck

i ck

139

Data In Hold Time after SCK

Falling Edge

—

x ck

i ck

SSI Timing

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56156ROM Datasheet(PDF) 44 Page - Motorola, Inc

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