DSP56156ROM datasheet(8/76 Pages) MOTOROLA

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DSP56156 Data Sheet

MOTOROLA

Pin Descriptions

TA (Transfer Acknowledge) — active

low input.

If there is no external bus ac-

tivity, the TA input is ignored by the

DSP. When there is external bus cycle

activity, TA can be used to insert wait

states in the external bus cycle. TA is

sampled on the leading edge of the

clock. Any number of wait states from 1

to infinity may be inserted by using TA.

If TA is sampled high on the leading

edge of the clock beginning the bus cy-

cle, the bus cycle will end 2T after the

TA has been sampled low on a leading

edge of the clock; if the Bus Control Reg-

ister (BCR) value does not program

more wait states. The number of wait

states is determined by the TA input or

by the Bus Control Register (BCR),

whichever is longer. TA is still sampled

during the leading edge of the clock

when wait states are controlled by the

BCR value. In that case, TA will have to

be sampled low during the leading edge

of the last period of the bus cycle pro-

grammed by the BCR (2T before the end

of the bus cycle programmed by the

BCR) in order not to add any wait states.

TA should always be deasserted during

t3 to be sampled high by the leading

edge of T0. If TA is sampled low (assert-

ed) at the leading edge of the t0 begin-

ning the bus cycle, and if no wait states

are specified in the BCR register, zero

wait states will be inserted in the exter-

nal bus cycle, regardless the status of

TA during the leading edge of T2.

BR (Bus Request) — active low output

when in master mode, active low in-

put when in slave mode.

After power-

on reset, this pin is an input (slave

mode). In this mode, the bus request

BR allows another device such as a pro-

cessor or DMA controller to become

the master of the DSP external data

bus D0-D15 and external address bus

A0-A15. The DSP asserts BG a few T

states after the BR input is asserted.

The DSP bus controller releases control

of the external data bus D0-D15, ad-

dress bus A0-A15 and bus control pins

PS/DS, RD, WR, and R/W at the earli-

est time possible consistent with prop-

er synchronization. These pins are then

placed in the high impedance state and

Bus Control

T0 T1 T2 T3 T0 T1 T2 Tw T2 T3 T0 T1 T2 T3 T0 T1 T2 Tw T2 Tw T2 T3

T0 T1 T2 Tw T2 Tw T2 Tw T2 T3 T0 T1 T2 Tw T2 Tw T2 T3 T0 T1 T2

CLKO

Figure 3 TA Controlled Accesses

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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