| Electronic Components Datasheet Search |
|
DSP56156ROM Datasheet(PDF) 27 Page - Motorola, Inc |
|
|
|||||||||||||||||||||||||||||
DSP56156ROM Datasheet(HTML) 27 Page - Motorola, Inc |
|
27 / 76 page ![]() AC Electrical Characteristics and Timing MOTOROLA DSP56156 Data Sheet 27 Table 14 Wait and Stop Timings Num Characteristics 40 MHz 50 MHz 60 MHz Unit Min Max Min Max Min Max 30 DR Asserted to CLK high (Setup Time for Synchronous Recovery from Wait State) 10 cyc - 4 9 cyc - 3 8 cyc - 2 ns 31 CLK high to DSO (ACK) Valid (Enter Debug Mode) after Syn- chronous Recovery from Wait State 18 cyc — 18 cyc — 18 cyc — ns 32 DR to DSO (ACK) Valid (Enter Debug Mode) - After Asynchronous Recovery from Stop State - After Asynchronous Recovery from Wait State 29 cyc 18 cyc — — 29 cyc 18 cyc — — 29 cyc 18 cyc — — ns ns 33 DR Assertion Width - to Recover from Wait/Stop without entering debug mode - to Recover from Wait/Stop short wake-up and enter debug mode - to Recover from Stop long wake-up and enter debug mode 12 29 cyc 262157 cyc 10 cyc — — 11 29 cyc 262157 cyc 10 cyc — — 10 29 cyc 262157 cyc 10 cyc — — ns ns ns Figure 15 Recovery from Wait State Using DR Pin — Synchronous Timing DR (input) DSO (output) 33 32 33 Reset, Stop, Wait, Mode Select, and Interrupt Timing Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |