DSP56156ROM datasheet(68/76 Pages) MOTOROLA

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Design Considerations

MOTOROLA

DSP56156 Data Sheet

Host Port

Considerations

Careful synchronization is required when

reading multi-bit registers that are written by

another asynchronous system. This is a com-

mon problem when two asynchronous sys-

tems are connected. The situation exists in

the host interface. The considerations for

proper operation are discussed below.

Host Programming

Considerations

1. Unsynchronized Reading of

Receive Byte Registers

When reading receive byte registers,

RXH or RXL, the host program should

use interrupts or poll the RXDF flag

which indicates that data is available.

This assures that the data in the receive

byte registers will be stable.

2. Overwriting Transmit Byte Registers

The host program should not write to the

transmit byte registers, TXH or TXL, un-

less the TXDE bit is set indicating that the

transmit byte registers are empty. This

guarantees that the transmit byte regis-

ters will transfer valid data to the HRX

3. Synchronization of Status Bits from

DSP to Host

HC, HREQ, DMA, HF3, HF2, TRDY,

TXDE, and RXDF status bits are set or

cleared from inside the DSP and read by

the host processor (refer to DSP56156 Us-

er’s Manual, I/O Interface section, Host/

DMA Interface Programming Model for

descriptions of these status bits). The

host can read these status bits very quick-

ly without regard to the clock rate used

by the DSP, but the possibility exists that

the state of the bit could be changing dur-

ing the read operation. This is generally

not a system problem, since the bit will

be read correctly in the next pass of any

host polling routine.

However, if the host asserts HEN for

more than timing number 101 (T101),

with a minimum cycle time of timing

number 103 (T103), then these status bits

are guaranteed to be stable. Care must

be exercised when reading status bits

HF3 and HF2 as an encoded pair. If the

DSP changes HF3 and HF2 from 00 to 11,

there is a small probability that the host

could read the bits during the transition

and receive 01 or 10 instead of 11. If the

combination of HF3 and HF2 has signif-

icance, the host could read the wrong

combination. Therefore, read the bits

twice and check for consensus.

4. Overwriting the Host Vector

The host program should change the

Host Vector register only when the Host

Command bit (HC) is clear. This change

will guarantee that the DSP interrupt

control logic will receive a stable vector.

5. Cancelling a Pending Host Command

Exception

The host processor may elect to clear the

HC bit to cancel the host command ex-

ception request at any time before it is

recognized by the DSP. Because the host

does not know exactly when the excep-

tion will be recognized (due to exception

processing synchronization and pipeline

delays), the DSP may execute the host

command exception after the HC bit is

cleared. For these reasons, the HV bits

must not be changed at the same time

that the HC bit is cleared.

Host Port Considerations

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56156ROM Datasheet(PDF) 68 Page - Motorola, Inc

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