GC4116 datasheet(21/57 Pages) ETC

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GC4116 MULTI-STANDARD QUAD DUC CHIP

DATA SHEET REV 1.0

- 16 -

APRIL 27, 2001

This document contains preliminary information which may be changed at any time without notice

The 2 bit sync mode control for each sync circuit is

defined in Table 1:

NOTE: the internal syncs are active high. The SIA and

SIB inputs have been inverted to be the active high syncs

SIA and SIB in Table1.

The ONE_SHOT sync (address 0, bit 7) can either be a

level or a pulse as selected by the OS_MODE control bit in

address 13. The level mode is used to initialize the chip, the

pulse mode is used to synchronously switch frequency,

phase or gain values.

The SIA and SIB external sync inputs are provided to

allow independent synchronization of different features of the

GC4116 chip. Sync mode 1 is either SIA or SIB, depending

upon what circuit is being synchronized by the sync circuit.

Table 2 lists all of the sync circuits, what they do, which sync

mode 1 it uses, and the suggested default mode settings.

The SIA sync is intended to be used during initialization

only. The circuits connected to SIA are ones that should be

initialized once, and then let free run. SIB is intended to be

used for those circuits which may be periodically initialized,

such as changing frequency, phase and gain between TDMA

bursts.

The interpolation control counter generates the request

strobe (CHREQ) output from the chip. This counter can be

syncronized using the input SIA sync (INT_SYNC=1). This

allows the user to lock the timing of the request strobe to the

SIA timing. If this is done, and BIG_SHIFT is even, then the

CHREQ strobe will go high 8 clock cycles after the SIA

strobe. For example, if the SIA signal is active during clock

cycle 0, then CHREQ will go high during clock cycle 8 and

then repeat every 4N clocks (or 2N clocks in the real input

mode) thereafter. If BIG_SHIFT is odd then the delay is 7

clock cycles.

3.12

INITIALIZATION

Two initialization procedures are recommended. The

first is recommended for multi-GC4116 chip configuration.

The second can be used for stand alone GC4116 chips.

Table 1: Sync Modes

MODE

SYNC SOURCE

off (never asserted)

SIA or SIB (See Table 2)

TC (terminal count of the sync counter)

or ONE_SHOT (if USE_ONESHOT in

address 0 is set)

on (always active)

Table 2: Sync Descriptions

Sync Circuit

Mode 1

Description

Default

INT_SYNC

SIA

Interpolation control counter.

Sets timing of CHREQ.

1(SIA)

COUNTER_

SYNC

SIA

Internal sync counter.

Generates TC sync. Mode 2

is always ONE_SHOT

2 (OS)

OUTPUT_

SYNC

SIA

The output sync (SO)

selection.

2 (TC)

GAIN_SYNC

SIB

A single bit sync selection.

GAIN_SYNC=0 means the

gain is applied immediately.

GAIN_SYNC=1 means the

gain is applied after SIB.

DIAG_SYNC

SIA

Selects when to start the

diagnostic ramp and to store

the diagnostic checksum.

2 (TC)

FREQ_SYNC

SIB

Selects when new frequency

settings take effect.

3 (on)

PHASE_SYNC

SIB

Selects when new phase

settings take effect.

3 (on)

NCO_SYNC

SIB

Reset the NCO phase

accumulator

0 (off)

DITHER_

SYNC

SIB

Clears the NCO dither circuit.

0 (off)

FLUSH _

(A,B,C,D)

SIA

Starts a ﬂush of the channel

1 (SIA)

ROCK_SYNC

SIA

Syncs the resampler’s serial

output clock. Mode 2 is SIB.

1 (SIA)

SCCK_SYNC

SIA

Syncs the serial controller’s

serial output clock. Mode 2 is

SIB.

1 (SIA)

RES_SYNC

Note 1

Syncs the resampler during

initialization

2 (SIA)

RATIO_SYNC

Note 1

Selects when a new

resampler ratio takes effect.

3 (SIB)

Note 1: These use a 3 bit sync mode selection where modes 0,1

and 5 are “off”, mode 2 is SIA, mode 3 is SIB, mode 4 is

ONE_SHOT, and modes 6 and 7 are “on”.

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