GC4116 datasheet(40/57 Pages) ETC

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GC4116 MULTI-STANDARD QUAD DUC CHIP

DATA SHEET REV 1.0

- 35 -

APRIL 27, 2001

This document contains preliminary information which may be changed at any time without notice

I/O CONTROL PAGE 5 (continue)

ADDRESS 17:

Resampler Input Mode Register

, suggested default = 0x03

ADDRESS 18:

Resampler Output Mode Register

, suggested default = 0x51

ADDRESS 19:

Sum IOMode Register

, suggested default = 0x80

BIT

TYPE

NAME

DESCRIPTION

0 LSB

R/W

RES_PACKED

Puts the resampler serial inputs into the 32 bit transfer mode where each

complex pair is packed into 32 bit words. The complex pair is formatted as I word

in the upper 16 bits and the Q word in the lower 16 bits. Each word is formatted

as MSB ﬁrst.

R/W

SC_MODE

Set to zero when the serial controller is being used with the resampler and is set

to 1 when it is used with the channels.

R/W

RCK_POL

The RIN Input bits and RFS frame strobes are clocked in on the trailing edge of

RSCK when this bit is set. The rising edge is used when this bit is low.

R/W

RFS_POL

The RFS signal is treated as active low when this bit is set. Otherwise the signal

is treated as active high.

R/W

RES_PARALLEL_A

The parallel/Serial control for resampler input A. When low input for resampler

channel A is taken from the serial port. When high it is taken from the resampler

input page registers.

R/W

RES_PARALLEL_B

The parallel/Serial control for resampler channel B.

R/W

RES_PARALLEL_C

The parallel/Serial control for resampler channel C.

R/W

RES_PARALLEL_D

The parallel/Serial control for resampler channel D.

BIT

TYPE

NAME

DESCRIPTION

0-3 LSB

R/W

ROCK_RATE

The resampler serial output clock rate is ROCK = CK/(1+ROCK_RATE). The

serial clock changes on the rising edge of CK when ROCK_RATE is even.

R/W

ROCK_POL

Resampler serial output clock polarity. Inverts ROCK. When ROCK_POL=0 and

ROCK_RATE=0, ROCK is a slightly delayed version of CK.

R/W

ROFS_POL

Resampler frame strobe polarity. If low, the frame strobe pulses high for one

RCK period prior to the ﬁrst transmitted bit. If high the frame strobe pulses low.

6,7

R/W

ROCK_SYNC

Sync control for the resampler output clock. The sync settings are 0 =never; 1 =

SIA; 2 =SIB; 3=Always.

BIT

TYPE

NAME

DESCRIPTION

0-2 LSB

R/W

SUM_ROUND

Round the output to 22-(2*SUM_ROUND) bits. The remaining low order bits are

cleared. In normal use SUM_ROUND is 0 for all chips in a sum path except the

ﬁnal one. The ﬁnal one is programmed to match the number of bits used by the

D/A or other follow-on devices.

3-5

R/W

SUM_SCALE

Shift the sum output up by SUM_SCALE bits prior to rounding. In normal use

SUM_SCALE is 0 for all chips in a sum path except the ﬁnal one. The ﬁnal one is

typically programmed so that the output has a 14 dB crest factor.

R/W

SUM_DELAY

The latency sumin to sumout is 8 cycles. Enabling this bit adds 8 cycles of

latency to the output of the 4 internal channels to match the delay from one

previous chip.

R/W

SUM_CLEAR

Clears sumin data so that regardless of the input to the sumin port it does not

affect the sum output.

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