GC4116 datasheet(7/57 Pages) ETC

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GC4116 MULTI-STANDARD QUAD DUC CHIP

DATA SHEET REV 1.0

- 2 -

APRIL 27, 2001

This document contains preliminary information which may be changed at any time without notice

3.0

FUNCTIONAL DESCRIPTION

The GC4116 quad transmit chip contains four identical

up-conversion channels. The up-convert channels accept

real or complex signals, interpolate them by programmable

amounts ranging from 32 to 5,792, and modulates them up

to selected center frequencies. The modulated signals are

then

summed

together

and

optionally

summed with

modulated signals from other GC4116 chips. Channels can

be used in pairs to reduce the interpolation ratio down to 16

in order to process wider band input signals.

Each channel contains a user programmable input filter

(PFIR) which can be used to shape the transmitted signal’s

spectrum, or can be used as a Nyquist transmit filter for

shaping digital data such as QPSK, GMSK or QAM symbols

(See Section 7 for example applications).

The up-converter channels are designed to maintain

over 115 dB of spur free dynamic range. Each up-convert

channel accepts 16 bit inputs (bit serial) and produces 20 bit

outputs. The up-converter outputs are summed with an

external 22 bit input to produce a single 22 bit output. The

chip can output either real or complex data. The frequencies

and phase offsets of the four sine/cosine sequence

generators can be independently specified, as can the gain

of each circuit. Each channel interpolates by the same

amount, but can be programmed with independent PFIR

coefficients. Channels can be synchronized to support

beamformed or frequency hopped systems.

An independent resampler block performs resampling

on up to 4 signals. The resampler has its own input and

output pins so that it can be used independently from the

up-convert channels. The resampler engine is identical to the

one in the gc4016. It provides a user programmable filter up

to 512 taps long and allows for sampling by arbitrary

amounts with delay resolutions up to 64 time phases.

A serial controller block is used to generate serial clocks

and frame strobes for the channel and resampler input ports.

This block simplifies interfacing the GC4116 to other

devices.

On chip diagnostic circuits are provided to simplify

system debug and maintenance.

The chip receives configuration and control information

over a microprocessor compatible bus consisting of an 8 bit

data I/O port, a 5 bit address port, a chip enable strobe, a

read strobe and a write strobe. The chip’s 110 control

registers (8 bits each) and five coefficient RAM’s are memory

mapped into the 5 bit address space of the control port using

an internal page register.

3.1

CONTROL INTERFACE

The chip is configured by writing control information into

control registers within the chip. The control registers are

grouped into 8 global registers and 64 pages of registers,

each page containing up to 16 registers. The global registers

are accessed as addresses 0 through 15. Address 15 is the

page register which selects which page is accessed by

addresses 16 through 31. The contents of these control

registers and how to use them are described in Section 5.

The registers are written to or read from using the

C[0:7], A[0:4], CE, RD and WR pins. Each control register

has been assigned a unique address within the chip. This

interface is designed to allow the GC4116 chip to appear to

an external processor as a memory mapped peripheral (the

pin RD is equivalent to a memory chip’s OE pin).

An external processor (a microprocessor, computer, or

DSP chip) can write into a register by setting A[0:4] to the

desired register address, selecting the chip using the CE pin,

setting C[0:7] to the desired value and then pulsing WR low.

The data will be written into the selected register when both

WR and CE are low and will be held when either signal goes

high. An alternate “edge write” mode can be used to strobe

the data into the selected register when either WR or CE

goes high. This is useful for processors that do not guarantee

valid data when the write strobe goes active, but guarantee

that the data will be stable for the required set up time before

the write strobe goes inactive. The edge write is necessary

for these processors, as some control registers (such as

most sync registers) are sensitive to transient values on the

C[0:7] data bus.

To read from a control register the processor must set

A[0:4] to the desired address, select the chip with the CE pin,

and then set RD low. The chip will then drive C[0:7] with the

contents of the selected register. After the processor has

read the value from C[0:7] it should set RD and CE high. The

C[0:7] pins are turned off (high impedance) whenever CE or

RD are high or when WR is low. The chip will only drive these

pins when both CE and RD are low and WR is high.

One can also ground the RD pin and use the WR pin as

a read/write direction control and use the CE pin as a control

I/O strobe. Figure 2 shows timing diagrams illustrating both

I/O modes.

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