MEGAWIN

MLC0xxB Series Technical Summary

11

Interrupt Registers

NMI select flag

Address

Register

7

6

5

4

3

2

1

0

R

W

00C0H

NMI_SEL

-

-

-

-

-

NIS2

NIS1

NIS0

√

√

NIS2

NIS1

NIS0

Selected NMI source

0

0

0

None (default)

0

0

1

TM0

0

1

0

DIV0x

0

1

1

P0

1

0

0

TM1

1

0

1

TM2

1

1

0

DIV1x

1

1

1

(None)

This register is used to select the NMI trigger source. The NMI is a rare resource of this system.

Only one trigger source is selected at one application is recommended. If over one trigger source is

occurs, program has to read NMI_SEL register to know which source triggering NMI.

IRQ enable flag

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

00C2H

IRQ_EN

-

-

DIV1x

TM2

TM1

P0

TM0

DIV0x

-

√

Program can enable or disable the ability of triggering IRQ through this register.

0: Disable (default “0” at initialization)

1: Enable

P0: Raising or falling edge occurs at port 0 input mode

TM0, TM1, TM2: Timer 0/1/2 underflow

DIV0x, DIV1x: Divider 0/1 selected interrupt frequency occurred

IRQ status flag (same address with IRQ_EN)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

00C2H

IRQ_ST

-

-

DIV1x

TM2

TM1

P0

TM0

DIV0x

√

-

When IRQ occurs, program can read this register to know which source triggering IRQ.

IRQ clear flag

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

00C3H

IRQ_CLR

-

-

DIV1x

TM2

TM1

P0

TM0

DIV0x

-

√

Program can clear the interrupt event by writing ‘1’ into the corresponding bit.