M83 datasheet(49/441 Pages) MITSUBISHI

49 / 441 page

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development

Rev.B2 for proof reading

Mitsubishi Microcomputers

M32C/83 group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Processor Mode

0 0 : Multiplexed bus is not used

0 1 : Allocated to CS2 space

0 1 : Allocated to CS1 space

1 1 : Allocated to entire CS space

(Note 5)

Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register.

Note 2: Do not set the processor mode bits and other bits simultaneously when setting the processor

mode bits to 012 or 112 . Set the other bits first,and then change the processor mode bits.

Note 3: When using 16-bit bus width in DRAM controler, must set this bit to "1".

Note 4: Valid in microprocessor and memory expansion modes 1, 2 and 3. Do not use multiplex bus

when mode 0 is selected. Do not set to allocated to CS2 space when mode 2 is selected.

Note 5: After the reset has been released, the M32C/83 group MCU operates using the separate bus. As

a result, in microprocessor mode, you cannot select the full CS space multiplex bus.

When you select the full CS space multiplex bus in memory expansion mode, the address bus

operates with 64 Kbytes boundaries, for each chip select.

Mode 0: Multiplexed bus cannot be used.

Mode 1: CS0 to CS2 when you select full CS space.

Mode 2: CS0 to CS1 when you select full CS space.

Mode 3: CS0 to CS3 when you select full CS space.

Note 6: No BCLK is output in single chip mode even when "0" is set in PM07. When stopping clock

output in microprocessor or memory expansion mode, make the following settings: PM07="1", bit 0

(CM00) and bit 1 (CM01) of system clock control register 0 (address 000616) = "0". "L" is now

output from P53.

Note 7: When selecting BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".

Symbol

Address

When reset

PM0

000416

8016 (CNVss = "L")

0316 (CNVss = "H")

Processor mode register 0 (Note 1)

b1 b0

b5 b4

0: RD / BHE / WR

1: RD / WRH / WRL

PM00

PM01

PM02

(Note 3)

(Note 2)

PM03

Software reset bit

R/W mode select bit

PM04

PM05

0 0: Single-chip mode

0 1: Memory expansion mode

1 0: Must not be set

1 1: Microprocessor mode

Must always be set to "0"

PM07

BCLK output disable bit

(Note 6)

Reserved bit

0 : BCLK is output

(Note 7)

1 : Function set by bit 0,1 of system

clock control register 0

The device is reset when this bit is

set to "1". The value of this bit is "0"

when read

Bit name

Function

Bit

symbol

Processor mode bit

Multiplexed bus space

select bit

(Note 4)

Figure 1.6.1. Processor mode register 0

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