M83 datasheet(78/441 Pages) MITSUBISHI

78 / 441 page

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development

Rev.B2 for proof reading

Mitsubishi Microcomputers

M32C/83 group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Power Saving

(3) Stop mode

All oscillation, main clock, subclock, and PLL synthesizer stop in this mode. Because the oscillation of

BCLK and peripheral clock stops in stop mode, peripheral functions such as the A-D converter, timer A

and B, serial I/O, intelligent I/O and watchdog timer do not function.

The content of the internal RAM is retained provided that VCC remains above 2.5V.

When changing to stop mode, the main clock division register (000C16) is set to “XXX010002” (division by

8 mode).

(a) Changing to stop mode

All clock stop control bit of system clock control register 1 (bit 0 at address 000716)

0: Clock ON

1: All clocks off (stop mode)

Before changing to stop mode, set bit 7 of PLL control register 0 (address 037616) to "0" to stop PLL.

Also, set bit 0 of VDC control register for PLL (address 001716) to "1" to turn PLL circuit power off.

(b) The status of the ports in stop mode

Table 1.8.7 shows the status of the ports in stop mode.

Stop mode is cancelled by a hardware reset or interrupt. If a peripheral function interrupt is used to

cancel stop mode, set the following registers.

• Interrupt priority set bits for exiting a stop/wait state of exit priority register (bits 0 to 2 at address 009F16) :RLVL0 to RLVL2

Set the same level as the flag register (FLG) processor interrupt level (IPL).

• Interrupt priority set bits of interrupt control register (bits 0 to 2)

Set to a priority level above the level set by RLVL0 to RLVL2 bits

• Interrupt enable flag of FLG register

I = 1

When exiting from stop mode using peripheral interrupt request, CPU operates the following BCLK

and the relevant interrupt routine is executed.

• When subclock was set as BCLK before changing to stop mode, subclock is set to BCLK after

cancelled stop mode

• When main clock was set as BCLK before changing to stop mode, the main clock division by 8 is set

to BCLK after cancelled stop mode.

Table 1.8.7. Port status during stop mode

Memory expansion mode

Single-chip mode

Microprocessor mode

_______

Address bus, data bus, CS0 to CS3, BHE

Retains status before stop mode

_____

______

________

_________

______

_________

________

RD, WR, WRL, WRH, DW, CASL, CASH

“H” (Note)

________

RAS

“H” (Note)

__________

HLDA, BCLK

“H”

ALE

“H”

Port

Retains status before stop mode

CLKOUT

When fc selected

“H”

When f8, f32 selected

Retains status before stop mode

________

Note :When self-refresh is done in operating DRAM control, CAS and RAS becomes “L”.

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