M83 datasheet(89/441 Pages) MITSUBISHI

89 / 441 page

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development

Rev.B2 for proof reading

Mitsubishi Microcomputers

M32C/83 group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupts

Table 1.9.3. Interrupt causes (variable interrupt vector addresses) (2/2)

Softwear interrupt number

Vector table address

Interrutp source

Address(L)to address(H) (Note 1)

Softwear interrupt number 55

+220 to +223 (00DC16 to 00DF16) Softwea interrupt

Softwear interrupt number 56

+224 to +227 (00E016 to 00E316) Softwea interrupt

Softwear interrupt number 57

+228 to +231 (00E416 to 00E716) Intelligent I/O interrupt 11/CAN interrupt 2

Softwear interrupt number 58 (Note 2) +232 to +235 (00E816 to 00EB16)

Softwea interrupt

Softwear interrupt number 63

+252 to +255 (00FC16 to 00FF16)

Note 1: Address relative to address in interrupt table register (INTB).

Note 2: Cannot be masked by I flag.

Note 3: When IIC mode is selected, NACK/ACK, start/stop condition detection interrupts are selected. The fault error

____

interrupt is selected when SS pin is selected.

Interrupt request reception

The following lists the conditions under which an interrupt request is acknowledged:

• Interrupt enable flag (I flag)

= 1

• Interrupt request bit

= 1

• Interrupt priority level

> Processor interrupt priority level (IPL)

The interrupt enable flag (I flag), the processor interrupt priority level (IPL), interrupt request bit and

interrupt priority level select bit are all independent of each other, so they do not affect any other bit.

There are I flag and IPL in flag register (FLG). This flag and bit are described below.

Interrupt Enable Flag (I Flag) and processor Interrupt Priority Level (IPL)

I flag is used to disable/enable maskable interrupts. When this flag is set (= 1), all maskable interrupts

are enabled; when the flag is cleared to 0, they are disabled. This flag is automatically cleared to 0

after a reset.

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from

level 0 to level 7.

If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt

is enabled.

Table 1.9.4 shows interrupt enable levels in relation to the processor interrupt priority level (IPL).

Table 1.9.4. IPL and Interrupt Enable Levels

Processor interrupt priority level (IPL)

Enabled interrupt priority levels

IPL2

IPL1

IPL0

Interrupt levels 1 and above are enabled.

Interrupt levels 2 and above are enabled.

Interrupt levels 3 and above are enabled.

Interrupt levels 4 and above are enabled.

Interrupt levels 5 and above are enabled.

Interrupt levels 6 and above are enabled.

Interrupt levels 7 and above are enabled.

All maskable interrupts are disabled.

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