Carefully observe the PC board layout guidelines to

ensure that noise and DC errors do not corrupt the cur-

rent-sense signals seen by LX and PGND. The IC must

be mounted close to the low-side MOSFET with short,

direct traces making a Kelvin-sense connection to the

source and drain terminals. See the PC Board Layout

section.

Voltage Positioning

The Quick-PWM control architecture responds virtually

instantaneously to transient load changes and elimi-

nates the control loop delay of conventional PWM con-

trollers. Therefore, a large portion of the voltage

deviation during a step load change is from the ESR

(equivalent series resistance) of the output capacitors.

For DDR termination applications, the maximum

allowed voltage deviation is

±40mV for any output load

transition from sourcing current to sinking current.

Passive voltage positioning adjusts the converter’s out-

put voltage based on its load current to optimize tran-

sient response and minimize the required output

capacitance.

Voltage positioning is implemented by connecting a

MOSFET Drivers

The DH and DL drivers are optimized to drive

MOSFETs that can deliver up to 25A output current. An

adaptive dead-time circuit monitors the DL output and

prevents the high-side MOSFET from turning on until

DL is fully off. There must be a low-resistance, low-

inductance path from the DL driver to the MOSFET gate

in order for the adaptive dead-time circuit to work prop-

erly. Otherwise, the sense circuitry in the MAX8553/

MAX8554 can interpret the MOSFET gate as “off” while

there is actually still charge left on the gate. Use very

short, wide traces measuring 10 squares to 20 squares

(50 mils to 100 mils wide if the MOSFET is 1in from the

MAX8553/MAX8554). This adaptive dead-time delay is

in addition to a fixed delay of 30ns (typ). The dead time

at the other edge (DH turning off) is determined by a

fixed 32ns (typ) internal delay.

Design Procedure

Setting the Output Voltage

For the MAX8554, the output voltage can be adjusted

from 600mV to 3.5V using a resistive voltage-divider

(R2 and R3 in Figures 1 and 3). To set the voltage,

choose a value for R3 in the range of 1k

Ω to 10kΩ, then

solve for R2 using the following equation:

Inductor Selection

Three key inductor parameters must be specified:

between size and efficiency is to set the inductor peak-

to-peak ripple current equal to 30% of the maximum

load current, thus LIR = 0.3. The switching frequency,

input voltage, output voltage, and selected LIR deter-

mine the inductor value as follows:

value is not critical and can be adjusted in order to

make trade-offs among size, cost, and efficiency.

Lower inductor values minimize size and cost and also

improve transient response but reduce efficiency and

increase output voltage ripple due to higher peak cur-

rents. Higher inductance increases efficiency by reduc-

ing the RMS current.

Find a low-loss inductor with the lowest possible DC

resistance that fits in the allotted dimensions. The

inductor’s current saturation rating must exceed the

L

VV

V

V

x f x I

x LIR

OUT

IN

OUT

IN

S

LOAD MAX

=

()

−

()

RR

V

V

OUT

FB

23

=









- 1

4.5V to 28V Input, Synchronous PWM Buck Controllers

for DDR Termination and Point-of-Load Applications

18

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