MAX8553EEE datasheet(21/24 Pages) MAXIM

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4.5V to 28V Input, Synchronous PWM Buck Controllers

for DDR Termination and Point-of-Load Applications

______________________________________________________________________________________

Setting Voltage Positioning

The droop resistor, RDRP (R4) in Figure 2, in series with

the output inductor before the output capacitor, sets the

droop voltage, VDRP. Choose RDRP such that the output

voltage at the maximum load current, including ripple, is

just above the lower limit of the output tolerance:

RDRP introduces some power dissipation, which is

given by:

RDRP should be chosen to handle this power dissipation.

Power MOSFET Selection

The MAX8553/MAX8554 drive external, logic-level, N-

channel MOSFETs as the circuit-switch elements. The

key selection parameters are:

On-resistance (RDS(ON)): The lower, the better.

Maximum drain-to-source voltage (VDSS): This

should be at least 20% higher than the input supply rail

at the high-side MOSFET’s drain.

Gate charges (QG, QGD, QGS): The lower, the better.

Choose the MOSFETs with rated RDS(ON) at VGS = 4.5V.

For a good compromise between efficiency and cost,

choose the high-side MOSFET that has a conduction

loss equal to switching loss at nominal input voltage and

maximum output current (see below). For the low-side

MOSFET, make sure that it does not spuriously turn on

because of the dV/dt caused by the high-side MOSFET

turning on, as this would result in shoot-through current

degrading the efficiency. MOSFETs with a lower QGD to

QGS ratio have higher immunity to dV/dt.

For proper thermal-management design, calculate the

power dissipation at the desired maximum operating

junction temperature, maximum output current, and

worst-case input voltage (for low-side MOSFET, worst

case is at VIN(MAX); for high-side MOSFET, it could be

either at VIN(MIN) or VIN(MAX)). The high-side MOSFET

and low-side MOSFET have different loss components

due to the circuit operation. The low-side MOSFET

operates as a zero voltage switch; therefore, major

losses are: the channel conduction loss (PLSCC), the

body-diode conduction loss (PLSDC), and the gate-

drive loss (PLSDR):

Use RDS(ON) at TJ(MAX):

where VF is the body-diode forward-voltage drop, tDT is

the dead time (~30ns), and fS is the switching frequency.

Because of the zero-voltage switch operation, low-side

MOSFET gate-drive loss occurs as a result of charging

and discharging the input capacitance (CISS). This loss

is distributed among the average DL gate driver’s

pullup and pulldown resistance, RDL (~1.2

Ω), and the

internal gate resistance (RGATE) of the MOSFET (~2

Ω).

The drive power dissipated is given by:

The high-side MOSFET operates as a duty-cycle con-

trol switch and has the following major losses: the

channel conduction loss (PHSCC), the VI overlapping

switching loss (PHSSW), and the drive loss (PHSDR).

The high-side MOSFET does not have body-diode con-

duction loss because the diode never conducts current.

LSDR

ISS

GATE

=×

() ××

LSDC

LOAD

=×

LSCC

OUT

LOAD

DS ON









() × ()

D DRP

DRP

OUT MAX

()

(

)

=×

()2

DRP

OUT TYP

OUT MIN

RIPPLE

OUT MAX

()

(

)

()

MAX8553

GND

FSEL

ILIM

REF

EN/HSD

REFIN

V+

POK

VTTR

VTT

PGND

BST

10k

Ω

2N7002

SDN

VIN

Figure 6. A resistor-divider (R1 and R2) is used to lower the

switching frequency.

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