4.5V to 28V Input, Synchronous PWM Buck Controllers

for DDR Termination and Point-of-Load Applications

______________________________________________________________________________________

23

Pin Configurations

outside using the top copper layer, while tying in

PGND and LX inside (underneath) the 8-pin SO

package.

5) When trade-offs in trace lengths must be made, it is

preferable to allow the inductor charging path to be

made longer than the discharge path. For example,

it is better to allow some extra distance between the

input capacitors and the high-side MOSFET than to

allow distance between the inductor and the low-

side MOSFET or between the inductor and the out-

put filter capacitor.

6) It may be desirable to deliberately introduce some

trace length (droop resistance) between the FB

inductor node and the output filter capacitor to

π).

7) Place feedback resistors as close as possible to

the IC.

8) Route high-speed switching nodes away from sen-

sitive analog nodes.

9) Make all pin-strap control input connections (ILIM,

etc.) to GND or VL close to the chip, and do not

connect to PGND.

Chip Information

TRANSISTOR COUNT: 2827

PROCESS: BiCMOS

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

EN/HSD

LX

DH

BST

PGND

DL

VL

V+

VTTR

TOP VIEW

MAX8553

QSOP

REFIN

POK

FSEL

VTT

ILIM

REF

GND

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

HSD

LX

DH

BST

PGND

DL

VL

V+

OUT

MAX8554

QSOP

EN

POK

FSEL

FB

ILIM

REF

GND