TLC3574, TLC3578, TLC2574, TLC2578

5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL

SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS

SLAS262C − OCTOBER 2000 − REVISED MAY 2003

14

POST OFFICE BOX 655303

CS trigger

PARAMETERS

MIN

TYP

MAX

UNIT

tsu(2)

Setup time, CS falling edge before SCLK rising edge, at 25-pF load

12

ns

td(4)

Delay time, delay time from the falling edge of 16th SCLK to CS rising edge, at 25 pF load

(see Note 12)

5

ns

tw(2)

Pulse width of CS high, at 25-pF load

1

tc(1)

td(5)

Delay time, delay from CS falling edge to MSB of SDO valid (reaches 90%

DVDD = 5 V

0

12

ns

td(5)

Delay time, delay from CS falling edge to MSB of SDO valid (reaches 90%

final level), at 10 pF load

DVDD = 2.7 V

0

30†

ns

td(6)

Delay time, delay from CS rising edge to SDO 3-state, at 10-pF load

0

6

ns

td(7)

Delay time, delay from CS falling edge to INT rising edge, at 10-pF load

DVDD = 5 V

0

6

ns

td(7)

Delay time, delay from CS falling edge to INT rising edge, at 10-pF load

DVDD = 2.7 V

0

16†

ns

† Specified by design

NOTE 12: For normal short sampling, td(4) is the delay time from the falling edge of 16th SCLK to CS rising edge.

For normal long sampling, td(4) is the delay time from the falling edge of 48th SCLK to CS rising edge.

Hi-Z

ID15

OD1

OD0

ID1

116

OD15

Don’t Care

ID0

OR

tsu(2)

td(4)

tw(2)

td(7)

td(5)

Hi-Z

Hi-Z

Don’t Care

VIH

VIL

CS

SCLK

SDI

SDO

EOC

INT

td(6)

Don’t Care

OD7

OD15

Normal sampling mode, CS initiates the conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK,

SDI) are inactive and are ignored.

Figure 2. Critical Timing for CS Trigger