TLC3574, TLC3578, TLC2574, TLC2578

5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL

SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS

SLAS262C − OCTOBER 2000 − REVISED MAY 2003

37

POST OFFICE BOX 655303

APPLICATION INFORMATION

interface with host

Figure 32 shows the examples of the interface between a single converter and host DSP (TMS320C54x

 DSP)

or microprocessor. The C54x is set as FWID=1 (active pulse width=1CLK); (R/X) DATDLY=1 (1 bit data delay);

CLK(X/R)P=0 (transmit data are clocked out at rising edge of CLK, receive data are sampled on falling edge

of CLK); and FS(X/R)P=1 (FS is active high). If multiple converters connect to the same C54x, use CS as chip

select.

The host microprocessor is set as the SPI master, CPOL=0 (active high clock), and CPHA=1 (transmit data is

clock out at rising edge of CLK, receive data are sampled at falling edge of CLK). 16 bits (or more) per transfer

is required.

FSR

FSX

DX

DR

CLKR

CLKX

IRQ

TMS320C54X

Converter

10 k

Ω

VDD

CS

FS

SDI

SDO

SCLK

INT/EOC

Ain

Single Converter Connects to DSP

SS

MOSI

MISO

SCK

IRQ

Host

Microprocessor

Converter

10 k

Ω

VDD

CS

FS

SDI

SDO

SCLK

INT/EOC

Converter Connects to Microprocessor

10 k

Ω

Ain

Figure 32. Typical Interface to Host DSP and Microprocessor

sampling time analysis

Figure 33 shows the equivalent circuit to evaluate the required sampling time. Req is the Thevenin equivalent

V

V

S

1–exp

–t

(sampling)

Req

C

(sampling)

Therefore, the required sampling time is

TMS320C54x is a trademark of Texas Instruments.