TLC3574, TLC3578, TLC2574, TLC2578

5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL

SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS

SLAS262C − OCTOBER 2000 − REVISED MAY 2003

15

POST OFFICE BOX 655303

FS trigger

PARAMETERS

MIN

TYP

MAX

UNIT

td(8)

Delay time, delay from CS falling edge to FS rising edge at 25-pF load

0.5

tc(1)

tsu(3)

Setup time, FS rising edge before SCLK falling edge at 25-pF load

0.25

×tc(1)

0.5

×tc(1)+ 5

ns

tw(3)

Pulse width of FS high, at 25-pF load

0.75

×tc(1)

tc(1)

1.25

×tc(1)

ns

td(9)

Delay time, delay from FS rising edge to MSB of SDO valid

DVDD = 5 V

26

ns

td(9)

Delay time, delay from FS rising edge to MSB of SDO valid

(reaches 90% final level), at 10-pF load

DVDD = 2.7 V

30†

ns

td(10) Delay time, delay from FS rising edge to next FS rising edge, at 25-pF load

Required

sampling time +

conversion time

ns

td(11)

Delay time, delay from FS rising edge to INT rising edge, at

DVDD = 5 V

0

6

ns

td(11)

Delay time, delay from FS rising edge to INT rising edge, at

10-pF load

DVDD = 2.7 V

0

16†

ns

† Specified by design

ID15

OD1

OD0

ID1

Hi-Z

1

16

OD15

ID0

Don’t Care

ID15

OD15

OR

td(10)

tw(3)

td(8)

tsu(3)

td(9)

td(11)

Don’t Care

Don’t Care

Don’t Care

Hi-Z

VIH

VIL

VOH

VOH

CS

FS

SCLK

SDI

SDO

EOC

INT

Normal sampling mode, FS initiates the conversion, CS can be tied to low. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK,

SDI) are inactive and are ignored.

Figure 3. Critical Timing for FS Trigger