TLC3574, TLC3578, TLC2574, TLC2578

5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL

SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS

SLAS262C − OCTOBER 2000 − REVISED MAY 2003

27

POST OFFICE BOX 655303

operation timing diagrams (continued)

12

3

5

46

7

13

14

15

16

1

ID15

1D14

ID13 1D12

12

ID15

ID14

ID11

ID10

ID9

ID4

ID3

ID2

ID1

ID0

OR

Don’t Care

CS

FS = High

SDI

INT

EOC

SDO

Hi-Z

The dotted lines means signal may or may not exist.

Figure 9. Write Cycle, CS Initiates Operation, FS = 1

FIFO READ Operation: When the FIFO is used, the first command after INT is generated is assumed to be

the FIFO READ. The first FIFO content is output immediately before the command is decoded. If this command

is not FIFO READ, the output is terminated. Using more layers of FIFO reduces the time taken to read multiple

conversion results, because the read cycle does not generate an EOC or INT, nor does it make a data

conversion. Once the FIFO is read, the entire contents in FIFO must be read out. Otherwise, the remaining data

is lost.

12

3

5

46

7

13

14

15

16

1

ID15

1D14

ID13

1D12

OD11 OD10 OD9

OD4

OD3

OD2

12

ID15

ID14

OD15 OD14 OD13 OD12

OD15 OD14

OR

SCLK

CS

FS = High

SDI

INT

EOC

SDO

OD[15:2] (for TLC3574/78) or OD[15:4](for TLC2574/78) is the FIFO content.

Don’t Care

Hi-Z

The dotted lines means signal may or may not exist.

Figure 10. FIFO Read Cycle, CS Initiates Operation, FS = 1