TLC3574, TLC3578, TLC2574, TLC2578

5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL

SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS

SLAS262C − OCTOBER 2000 − REVISED MAY 2003

17

POST OFFICE BOX 655303

circuit description

converter

The converters include a successive-approximation ADC utilizing a charge redistribution DAC. Figure 5 shows

a simplified block diagram of the ADC. The sampling capacitor acquires the signal on Ain during the sampling

period. When the conversion process starts, the control logic directs the charge redistribution DAC to add and

subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition.

When balanced, the conversion is complete and the ADC output code is generated.

Charge

Redistribution

DAC

Control

Logic

_

+

REFM

Ain

ADC Code

Figure 5. Simplified Block Diagram of the Successive-Approximation System

analog input range and internal test voltages

TLC3578 and TLC2578 have 8 analog inputs (TLC3574 and TLC2574 have 4) and three test voltages. The

inputs are selected by the analog multiplexer according to the command entered (see Table 1). The input

multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel

switching.

All converters are specified for bipolar input range of

±10 V. The input signal is scaled to 0–4 V at the SAR ADC

input via the bipolar scaling circuit (see the functional block diagram and the equivalent analog input circuit):

–10 V to 0 V, 10 V to 4 V, and 0 V to 2 V.

analog input mode

Two input signal modes can be selected: single-ended input and pseudodifferential input.

_

+

Charge

Redistribution

DAC

Control

Logic

Ain(+)

REFM

ADC Code

S1

Ain(−)

When sampling, S1 is closed and S2 connects to Ain(−).

During conversion, S1 is open and S2 connects to REFM.

Figure 6. Simplified Pseudodifferential Input Circuit

Pseudodifferential input refers to the negative input, Ain(−). Its voltage is limited in magnitude to

±1 V. The input

frequency limit of Ain(−) is the same as the positive input Ain(+). This mode is normally used for ground noise

rejection or dc offset.