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LM9811 Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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LM9811 Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 36 page  AC Electrical Characteristics, MCLK Independent The following specifications apply for AGND = DGND = DGND (I/O) = 0V, VA = VD = VD(I/O) = +5.0VDC, REF IN = +1.225VDC, f MCLK = 20MHz, tMCLK = 1/fMCLK,tr = tf = 5ns, Rs = 25Ω,CL(databus loading) = 50 pF/pin. Boldface limits apply for TA = TJ = T MIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions Typical Limits Units (Note 9) (Note 10) (Limits) f MCLK Maximum MCLK Frequency (Note 16) 20 MHz (min) Minimum MCLK Frequency 1 MHz (max) MCLK Duty Cycle 30 40 % (min) 70 60 % (max) t A SYNC Setup of MCLK 5 10 ns (min) t CDSETUP Correction Data Valid to CLK Setup 14 20 ns (min) t CDHOLD Correction Data Valid to CLK Hold −12 0 ns (min) t D1H,tD0H RD High to DD0–DD9 TRI-STATE 5 15 ns (max) t DACC Access Time Delay from RD Low to DD0–DD9 Data Valid 15 30 ns (max) f SCLK Maximum SCLK Frequency 8 MHz (min) SCLK Duty Cycle 40 % (min) 60 % (max) t SDI SDI Set-Up Time from SCLK Rising Edge 3 10 ns (min) t HDI SDI Hold Time from SCLK Rising Edge 2 15 ns (min) t DDO Delay from SCLK Falling Edge to SDO Data Valid 25 55 ns (max) t HDO SDO Hold Time from SCLK Falling Edge R L = 3k, CL = 25pF 30 55 ns (max) 5 ns (min) t DELAY DELAY from SCLK Falling Edge to CS Rising or Falling Edge 5 10 ns (min) t SETUP Set-Up Time of CS Rising or Falling Edge to SCLK Rising Edge 0 10 ns (min) t S1H,tS0H Delay from CS Rising Edge to SDO TRI-STATE R L = 3k, CL = 50pF 25 50 ns (max) t RDO SDO Rise Time, TRI-STATE to High R L = 3k, CL = 50pF 20 ns SDO Rise Time, Low to High 20 ns t FDO SDO Fall Time, TRI-STATE to Low R L = 3k, CL = 50pF 20 ns SDO Fall Time, High to Low 20 ns AC Electrical Characteristics, MCLK Dependent The following specifications apply for AGND = DGND = DGND (I/O) = 0V, VA = VD = VD(I/O) = +5.0VDC, REF IN = +1.225VDC, f MCLK = 20MHz, tMCLK = 1/fMCLK,tr = tf = 5ns, Rs = 25Ω,CL(databus loading) = 50 pF/pin. Refer to Table 2. Configuration Register Parameters for limits labelled C.R. Boldface limits apply for T A = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions Typical Limits Units (Note 9) (Note 10) (Limits) t START MCLK to first φ1 High 50ns 1 t MCLK tφ φ1, φ2 Clock Period Standard CCD Mode 400ns 8 t MCLK Even/Odd CCD Mode 800ns 16 t MCLK t TRWIDTH Transfer Pulse (TR) Width C.R. µs t GUARD φ1 to TR, TR to φ1 Guardband C.R. ns t RSWIDTH Reset Pulse (RS) Width C.R. ns t RS Falling Edge of φ1 to RS Standard CCD Mode C.R. ns Either Edge of φ1 to RS Even/Odd CCD Mode www.national.com 5 |
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