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LM9811 Datasheet(PDF) 17 Page - National Semiconductor (TI) |
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LM9811 Datasheet(HTML) 17 Page - National Semiconductor (TI) |
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17 / 36 page ![]() Configuration Register t MCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 20MHz (t MCLK = 50ns). Times for 12MHz MCLK can be calculated by multiplying by (Continued) TABLE 2. Configuration Register Parameters (Continued) Parameter Control Bits Result Sample Signal Position (t S/HSIG) SS3 SS2 SS1 SS0 0 0 0 0 0.0t MCLK (0ns) 0 0 0 1 0.5t MCLK (25ns) 0 0 1 0 1.0t MCLK (50ns) 0 0 1 1 1.5t MCLK (75ns) 0 1 0 0 2.0t MCLK (100ns) 0 1 0 1 2.5t MCLK (125ns) 0 1 1 0 3.0t MCLK (150ns) 0 1 1 1 3.5t MCLK (175ns) 1 0 0 0 4.0t MCLK (200ns) 1 0 0 1 4.5t MCLK (225ns) 1 0 1 0 5.0t MCLK (250ns) 1 0 1 1 5.5t MCLK (275ns) 1 1 0 0 6.0t MCLK (300ns) 1 1 0 1 6.5t MCLK (325ns) 1 1 1 0 7.0t MCLK (350ns) 1 1 1 1 7.5t MCLK (375ns) φ1 Enable φ1EN 0 φ1 Output Off 1 φ1 Output On φ2 Enable φ2EN 0 φ2 Output Off 1 φ2 Output On RS Enable RSEN 0 RS Output Off 1 RS Output On TR Enable TREN 0 TR Output Off 1 TR Output On TR Pulse Width (t TRWIDTH) TRW1 TRW0 0 0 20 t MCLK (1.0 µs) 0 1 30 t MCLK (1.5 µs) 1 0 40 t MCLK (2.0 µs) 1 1 50 t MCLK (2.5 µs) TR- φ1 TRGRD Guardband 0 1t MCLK (50ns) (t GUARD)1 2t MCLK (100ns) TR Polarity TRPOL 0 TR 1 TR Single Polarity SIGPOL 0 Positive (CIS) 1 Negative (CCD) www.national.com 17 |
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