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LM9811 Datasheet(PDF) 18 Page - National Semiconductor (TI) |
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LM9811 Datasheet(HTML) 18 Page - National Semiconductor (TI) |
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18 / 36 page ![]() Configuration Register t MCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 20MHz (t MCLK = 50ns). Times for 12MHz MCLK can be calculated by multiplying by (Continued) TABLE 2. Configuration Register Parameters (Continued) Parameter Control Bits Result Dummy Pixels Note: Minimum Register Value is 2. Actual number of dummy pixels in CCD should be one less than number in this register. BLS6 BLS5 BLS4 BLS3 BLS2 BLS1 BLS0 Dummy Pixels 0 000000 Not Valid 0 000001 Not Valid 0 000010 1 0 000011 2 • •••••• • 1 111101 124 1 111110 125 1 111111 126 Optical Black Pixels Note: Minimum Register Value is 1. BLL7 BLL6 BLL5 BLL4 BLL3 BLL2 BLL1 BLL0 Optical Black Pixels 0 0000000 Not Valid 0 0000001 1 0 0000010 2 0 0000011 3 • ••••••• • 1 1111101 253 1 1111110 254 1 1111111 255 Internal PGA Gain Coefficient GAIN7 GAIN6 GAIN5 GAIN4 GAIN3 GAIN2 GAIN1 GAIN0 dB [V/V] 0 0000000 0.00 1.000 0 0000001 0.07 1.008 0 0000010 0.13 1.015 • ••••••• • 1 1111101 9.35 2.935 1 1111110 9.37 2.942 1 1111111 9.40 2.950 PGA Gain PGASRC Coefficient 0 Internal Source 1 External Offset DAC Sign ODSIGN 0 Negative 1 Positive Power Down PD 0 Operating 1 Powered Down Offset Add OFF ADD 0 Offset z0 LSB 1 Offset z+8 LSB www.national.com 18 |
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