AT43USB370 datasheet(4/50 Pages) ATMEL

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AT43USB370

3340B–USB–12/03

Pin Description

Pin Name

Type

Description

A[7:0]

Input

ADDRESS BUS – System Address Bus

CS_N

Input

CHIP_SELECT – from System Processor. Active Low

OE_N

Input

OUTPUT_ENABLE – from System Processor. Active Low

SELECT

Input

PROCESSOR_SELECT – from System Processor – used to select between the USB Controller

(USBC) and System Interface Controller (SIC) when firmware is downloaded to these controllers

through the System Processor. Logic “1” selects SIC and Logic “0” selects USBC.

INTR_IN

Input

Interrupt to AT43USB370 – from System Processor. Active High

INTR_OUT

Output

Interrupt from AT43USB370 – to System Processor. Active High

VDD

Power Supply/Gnd

3.3V Power Supply

VSS

Power Supply/Gnd

Ground

VDD18

Power Supply/Gnd

1.8V Power Supply

PROG

Input

PROGRAM_LOAD_ENABLE – from System Processor – used when the program is

downloaded in the USB Controller and System Interface Controller through the System

Processor. Active High

Input

PIO Mode Handshake Signal – from System Processor. Active High

READY

Output

READY – to System Processor – used when the program is downloaded in the USB Controller

and System Interface Controller through the System Processor. Active High

DONE

Input

DONE – from System Processor – used when the program is downloaded in the USB Controller

and System Interface Controller through the System Processor. Active High

BUSY

Output

BUSY – to System Processor – used when the System Interface Controller is busy in an

interrupt service routine and does not want the System Processor to issue an interrupt. Active

High

WAIT_N

Output

WAIT – to System Processor. Active Low

WE_N

Input

WRITE_ENABLE – from System Processor. Active Low

DREQ_N

Output

DMA Request – to System Processor – used to signal to the System Processor that the

AT43USB370 wants to start a DMA transfer. Active Low

DACK_N

Input

DMA Acknowledge – from System Processor. Active Low

Input

BIST – Test Signal

Input

Memory – Test Signal

TP0

Input

Test Pin 0

TP1

Output

Test Pin 1

TP2

Input

Test Pin 2

TP3

Input

Test Pin 3

CLK_SEL

Input

External/PLL Clock Selection – Low selects crystal-PLL clock source while a High uses

XTAL1, bypassing the PLL.

XTAL1

Input

Oscillator Input – Input to the inverting oscillator amplifier.

XTAL2

Output

Oscillator Output – Output of the inverting oscillator amplifier.

LFT

Input

PLL Loop Filter – For proper operation of the PLL, this pin should be connected through a

2.2 nF capacitor in parallel with a 470

Ω resistor in series with a 22 nF capacitor to ground

(VSS). Both capacitors must be high quality ceramic.

AT43USB370 Datasheet(PDF) 4 Page - ATMEL Corporation

AT43USB370 Datasheet(HTML) 4 Page - ATMEL Corporation

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