AT43USB370 datasheet(6/50 Pages) ATMEL

6 / 50 page

AT43USB370

3340B–USB–12/03

Architectural

Overview

The AT43USB370 host/function processor is available in the SRAM version. It utilizes two on-

chip microcontrollers, the USB controller (USBC) and the System Interface Controller (SIC) to

off-load USB related processing from the system processor. On power-up or reset, the system

processor downloads the appropriate firmware into the USBC and SIC via the system bus

interface.

Functionally, the USBC manages the low-level USB protocol such as enumeration, frame

management and transaction scheduling, in addition to handling USB hub driver. The SIC pro-

vides data flow management to and from the system processor. It is responsible for

constructing USB packets of appropriate sizes, handling retries, channeling data to and from

FIFOs, and providing API support to the external system processor.

The USBC and the SIC share the same set of on-chip Control and Status Registers with the

System Processor Interface. The system interface logic makes use of this register set to facili-

tate data exchange between the AT43USB370 and the system processor. In a typical design

scenario, the AT43USB370 appears as a memory mapped peripheral to the system proces-

sor. Externally accessible registers are shown in Table 1 on page 11. The read and write

accesses to the system interface registers by the system processor are made through external

memory operations on the system bus.

The system processor connects to the AT43USB370 through the generic 32-bit system pro-

cessor interface. The system interface signals consist of an address bus, a data bus, a chip

select, a read enable and write enable. The on-chip DMA engine provides maximum data

throughput between the system processor and the on-chip USB FIFO blocks. The system pro-

cessor communicates with the DMA engine through standard DMA signaling.

The embedded USB hardware consists of a USB Transceiver, a Serial Interface Engine (SIE),

a SIE Controller, an SOF (Start of Frame) Generation and a FIFO block. The FIFO block is

divided into a 128-bytes control endpoint and 2 Kbytes of memory block dynamically config-

urable to support different data endpoint requirements.

The AT43USB370 can be configured to operate either in host mode or function mode. The

mode of operation is determined by writing corresponding values to the specified registers and

downloading the corresponding USBC and SIC firm ware to the AT43USB370. The

AT43USB370 commences its operation once it is configured.

The AT43USB370 requires an external 6-MHz crystal to provide a reference clock frequency

for the on-chip PLL. The PLL provides all of internal clock sources required for the

AT43USB370.

Please note that the AT43USB370 signals use level detection, not edge detection.

Functional

Description

USB Transceiver

A Universal Serial Bus Revision 2.0 compliant transceiver is embedded in the AT43USB370.

The transceiver provides the physical layer signaling and is capable of transmitting and receiv-

ing serial data at 12 Mbps and 1.5 Mbps. The driver portion of the transceiver is differential

while the receiver section is comprised of a differential and two single-ended receivers. Inter-

nally, the transceiver interfaces to the Serial Interface Engine. Externally, the transceiver

interfaces directly with the USB connectors and cables through external termination resistors.

AT43USB370 Datasheet(PDF) 6 Page - ATMEL Corporation

AT43USB370 Datasheet(HTML) 6 Page - ATMEL Corporation

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