ML9042 datasheet(9/58 Pages) LAPIS

9 / 58 page

FEDL9042-01

LAPIS Semiconductor

ML9042-xx

9/58

(GND = 0 V, VDD = 2.7 to 5.5 V, Ta = –40 to +85C)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Applicable

pins

Voltage Multiplier

Input Voltage

VMUL

Note 7

1.8

—

2.75

VIN

1/5

bias

4.3

—

(VDD–VIN)

 2

Voltage Multiplier

Output Voltage

VOUT

VDD = 2.7 V, VIN = 2.25 V

f = 175 kHz

A capacitor for the voltage

multiplier = 1 to 4.7

F

VOUT load current = 54 A

BE = “H”

Applied to LCD bias

resistance of 10 k

 (TYP)

only

1/4

bias

4.3

—

(VDD–VIN)

 2

VOUT

VLCD1

1/5

bias

2.7

—

5.5

Bias Voltage for

Driving LCD

VLCD2

V0–GND

Note 8

1/4

bias

2.7

—

5.5

Note 1:

Applied to the voltage drop occurring between any of the V0, V1, V4 and GND pins and any of

the common pins (COM1 to COM17) when the current of 4 A flows in or flows out at one

common pin.

Also applied to the voltage drop occurring between any of the V0, V2, V3A (V3B) and GND pins

and any of the segment pins (SEG1 to SEG100) when the current of 4 A flows in or flows out at

one segment pin.

The current of 4

A flows out when the output level is V

DD or flows in when the output level is

V5.

Note 2:

Applied to the current flowing into the VDD pin when the external clock (fOSC2 = fin = 270 kHz) is

fed to the internal Rf oscillation or OSC1 under the following conditions:

VDD = V0 = 5 V

GND = 0 V,

V1, V2, V3A (V3B) and V4: Open

E/SHTB and BE: “L” (fixed)

Other input pins: “L” or “H” (fixed)

Other output pins: No load

ML9042 Datasheet(PDF) 9 Page - LAPIS Semiconductor Co., Ltd.

ML9042 Datasheet(HTML) 9 Page - LAPIS Semiconductor Co., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Datasheet Download

Link URL