ML9042 datasheet(36/58 Pages) LAPIS

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FEDL9042-01

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ML9042-xx

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10) Busy Flag/Address Counter Read (Execution time: 0

s)

RS1

RS0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction code:

The “BF” bit (DB7) of this instruction tells whether the ML9042 is busy in internal operation (BF = “1”) or not

(BF = “0”).

When the “BF” bit is “1”, the ML9042 cannot accept any other instructions. Before inputting a new instruction,

check that the “BF” bit is “0”.

When the “BF” bit is “0”, the ML9042 outputs the correct value of the address counter. The value of the

address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the DDRAM, ABRAM and

CGRAM addresses is set in the counter is determined by the preceding address setting.

When the “BF” bit is “1”, the value of the address counter is not always correct because it may have been

incremented or decremented by 1 during internal operation.

11) DDRAM/ABRAM/CGRAM Data Read

RS1

RS0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Instruction code:

A character code (P7 to P0) is read from the DDRAM, Display-ON data (P7 to P0) from the ABRAM or a

character pattern (P7 to P0) from the CGRAM.

The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.

After data is read, the address counter (ADC) is incremented or decremented as set by the Entry Mode Setting

instruction (see 3).

Note: Conditions for reading correct data

(1)

The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read instruction is input.

(2)

When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see 5) is input

before this Data Read instruction is input.

(3)

When two or more consecutive RAM Data Read instructions are executed, the following read data is

correct.

Correct data is not output under conditions other than the cases (1), (2) and (3) above.

Note:

The execution time of this instruction is 37

s at an oscillation frequency (OSC) of 270 kHz.

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