ML9042 datasheet(34/58 Pages) LAPIS

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FEDL9042-01

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5) Cursor/Display Shift

RS1

RS0

DB7

DB6

DB5

DB4

DB3

S/C

DB2

R/L

DB1



DB0



Instruction code:

: Don’t Care

S/C = “0”, R/L = “0”

This instruction shifts left the cursor and blink positions by 1 (decrements the

content of the ADC by 1).

S/C = “0”, R/L = “1”

This instruction shifts right the cursor and blink positions by 1 (increments the

content of the ADC by 1).

S/C = “1”, R/L = “0”

This instruction shifts left the entire display by 1 character position. The cursor

and blink positions move to the left together with the entire display.

The Arbitrator display is not shifted.

(The content of the ADC remains unchanged.)

S/C = “1”, R/L = “1”

This instruction shifts right the entire display by 1 character position. The cursor

and blink positions move to the right together with the entire display.

The Arbitrator display is not shifted.

(The content of the ADC remains unchanged.)

In the 2-line mode, the cursor or blink moves from the first line to the second line when the cursor at digit 40

(27; hex) of the first line is shifted right.

When the entire display is shifted, the character pattern, cursor or blink will not move between the lines (from

line 1 to line 2 or vice versa).

Note:

The execution time of this instruction is 37

s at an oscillation frequency (OSC) of 270 kHz.

6) Function Setting

RS1

RS0

DB7

DB6

DB5

DB4

DB3

DB2

ABE

DB1

SSR

DB0

CSR

: Don’t Care

Instruction code:

(1)

When the “DL” bit (DB4) of this instruction is “1”, the data transfer to and from the CPU is performed

once by the use of 8 bits DB7 to DB0.

When the “DL” bit (DB4) of this instruction is “0”, the data transfer to and from the CPU is performed

twice by the use of 4 bits DB7 to DB4.

(2)

The 2-line display mode is selected when the “N” bit (DB3) of this instruction is “1”. The 1-line display

mode is selected when the “N” bit is “0”.

The arbitrator is displayed when the “ABE” bit (DB2) of this instruction is “1”.

The arbitrator is not displayed when the “ABE” bit (DB2) of this instruction is “0”.

(3)

The transfer direction of the segment signal output data is controlled.

When the “SSR” bit (DB1) of this instruction is “1”, the data is transferred from SEG100 to SEG1.

When the “SSR” bit (DB1) of this instruction is “0”, the data is transferred from SEG1 to SEG100.

The transfer direction of the common signal output data is controlled.

At 1/n duty,

When the “CSR” bit (DB0) of this instruction is “1”, the data is transferred from COMn to COM1.

When the “CSR” bit (DB0) of this instruction is “0”, the data is transferred from COM1 to COMn.

After the ML9042 is powered on, this function setting should be carried out before execution of any

instruction except the Busy Flag Read. After this function setting, no instructions other than the DL Set

instruction can be executed. In the Serial I/F Mode, DL setting is ignored.

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