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ML9042 Datasheet(PDF) 29 Page - LAPIS Semiconductor Co., Ltd. |
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ML9042 Datasheet(HTML) 29 Page - LAPIS Semiconductor Co., Ltd. |
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29 / 58 page ![]() FEDL9042-01 LAPIS Semiconductor ML9042-xx 29/58 Serial Interface Mode In the Serial I/F Mode, the ML9042 interfaces with the CPU via the RS0/CSB, E/SHTB, RW/SI, and DB0(SO) pins. Writing and reading operations are executed in units of 16 bits after the RS0/CSB signal falls down. If the RS0/CSB signal rises up before the completion of 16-bit unit access, this access is ignored. When the BF bit is “1”, the ML9042 cannot accept any other instructions. Before inputting a new instruction, check that the BF bit is “0”. Any access when the BF bit is “1” is ignored. Data format is LSB-first. Examples of Access in the Serial I/F Mode Note 1: Higher 5 bits of each instruction must be input at a “H” level. Note 2: Lower 8 bits are “don’t care” when the instructions in the READ MODE are set. Note 3: After one instruction is input, the next instruction must be input after the RS0/CSB pin is pulled at a “H” level. 1) WRITE MODE RS0/CSB E/SHTB BUSY RWB/SI DB(SO) 2) READ MODE RS0/CSB E/SHTB BUSY RWB/SI DB(SO) (Internal operation) (Internal operation) 12 12 34 56 78 1 13 14 15 16 9 101112 11 11 1 R/ W RS0 RS1 D0 D1 D2 D3 D4 D5 D6 D7 1 3 4 5 6 7 8 9 10111213141516 1 11 11 1 R/ W RS0 RS1 1 D0 D1 D2 D3 D4 D5 D6 D7 |
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