CS8904 datasheet(12/34 Pages) CIRRUS

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DS191PP2

CS8904

Crystal LAN™ Quad Ethernet Transceiver

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

3.0 THEORY OF OPERATION

3.1 Overview

The CS8904 provides four independent ports for a

multi-port Ethernet system logic device. In terms of

the

IEEE

802.3

specification,

the

CS8904

combines the functions of the Physical Signaling

sublayer (PLS) and the 10BASE-T Medium

Attachment Unit (MAU) for four independent

interface into a single device. Typically, the system

logic device provides multiple Media Access

Control (MAC) interfaces, which connect to the

CS8904. For simplicity, a single port interface of

this system logic device is referred to as a digital

controller throughout this datasheet.

A synchronous bit-serial stream of data is received

and transmitted between the CS8904 and the digital

controller. Digital information that is sent to the

CS8904 from the digital controller is Manchester

encoded and transmitted over the 10BASE-T

wiring system. Data received from the 10BASE-T

wiring system is converted to serial data which is

sent as a bit-serial stream, along with the clock

recovered from the data, to the Ethernet system

logic. Additionally, status and control information

is exchanged between the CS8904 and the Ethernet

digital controller. All ports operate independently,

allowing features such as duplex selection, Auto-

Negotiation, and loopback to operate on a per-port

basis.

The CS8904 also incorporates full IEEE-compliant

transmit and receive filtering internally. No

external filters are required and simple isolation

transformers may be used with the 10BASE-T

ports.

3.2 Encoder/Decoder (ENDEC)

The

CS8904’s

integrated

encoder/decoder

(ENDEC) circuit is compliant with the relevant

portions of clause 7 of the Ethernet standard

(ISO/IEC 8802-3, 1996). Its primary functions

include

performing

Manchester

encoding

transmit data, informing the controller when valid

receive data is present (Carrier Detection), and

recovering the clock and NRZ data from incoming

Manchester-encoded data.

Figure 4 provides a block diagram of the ENDEC

and illustrates how it interfaces to the digital

controller and 10BASE-T transceiver.

Encoder

Carrier

Detector

Decoder

& PLL

Clock

RxCLK

RxDATA

TxCLK

TxDATA

TxENBL

COLL

System

ASIC

ENDEC

10BASE-T

Transceiver

Figure 4. ENDEC

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