SC2200 datasheet(371/433 Pages) NSC

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Electrical Specifications (Continued)

Table 8-11. Memory Controller Timing Parameters

Symbol

Parameter

Min

Max

Unit

Control Output1,2 Valid from SDCLK[3:0]

Control output includes all the following signals: RASA#, CASA#, WEA#, CKEA, DQM[7:0], and CS[1:0]#.

Load = 50 pF, VCORE = 1.8V@ 233/266 MHz, VCORE = 2.0V@ 300 MHz, VIO =3.3V, @25

oC.

Use the Min/Max equations [value+(x * y)] to calculate the actual value.

x is the shift value which is applied to the SHFTSDCLK field, and y is 0.45 the core clock period.

Note that the SHFTSDCLK field = GX_BASE+Memory Offset 8404h[5:3]. Refer to the

GX1 Processor Series Datasheet

for more information.

For example, for a 266 MHz SC2200 running a 88.7 MHz SDRAM clock, with a shift value of 3:

t1 Min = -3.5 + (3 * (5 * 0.45)) = 3.25 ns

t1 Max = -1.0 + (3 * (5 * 0.45)) = 5.75 ns

-3.0 + (x * y)

0.1 + (x * y)

MA[12:0], BA[1.0] Output2 Valid from SDCLK[3:0]

-3.2 + (x * y)

0.1 + (x * y)

MD[63.0] Output2 Valid from SDCLK[3:0]

-2.2 + (x * y)

0.7 + (x * y)

MD[63.0] Read Data in Setup to SDCLK_IN

1.3

MD[63:0] Read Data Hold to SDCLK_IN

2.0

SDCLK[3:0], SDCLK_OUT cycle time

233 MHz

266 MHz

8.3

13.5

300 MHz

7.3

12.5

SDCLK[3:0], SDCLK_OUT fall/rise time between

(VOLD-VOHD)

2ns

SDCLK_IN fall/rise time between (VILD-VIHD)2

t10

SDCLK[3:0], SDCLK_OUT high time

233 MHz

4.0

266 MHz

3.0

300 MHz

2.5

t11

SDCLK[3:0], SDCLK_OUT low time

233 MHz

4.0

266 MHz

2.5

300 MHz

2.5

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