SC2200 datasheet(374/433 Pages) NSC

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374

Revision 3.0

Electrical Specifications (Continued)

8.3.3

CRT and TFT Interface

Table 8-13 and Figure 8-7 describe the timing of the digital CRT interface of the SC2200. All measurement points in this

table are identical to the voltage measurement levels described in Table 8-10 on page 369.

Note that signals DDC_SCL and DDC_SDA of the CRT interface are compliant with standard ACCESS.bus timing and are

controlled by software.

Figure 8-7. TFT Timing Diagram

Table 8-13. TFT Timing Parameters

Symbol

Parameter

Min

Max

Unit

Comments

tOV

TFTD[17:0], TFTDE valid time after TFTDCK rising

edge (multiplexed on IDE)

tOV

TFTD[17:0], TFTDE valid time after TFTDCK rising

edge (multiplexed on Parallel Port)

tCLK_RF

TFTDCK rise/fall time1 between 0.8V and 2.0V

Guaranteed by characterization

3ns

tCLK_P

TFTDCK period time (multiplexed on IDE)

tCLK_P

TFTDCK period time (muxed on Parallel Port)

12.5

tCLK_D

TFTDCK duty cycle

40/60

tOV

tCLK_RF

tCLK_P

TFTDCK

TFTD[17:0]

TFTDE

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