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SC2200 Datasheet(PDF) 376 Page - National Semiconductor (TI) |
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SC2200 Datasheet(HTML) 376 Page - National Semiconductor (TI) |
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376 / 433 page  www.national.com 376 Revision 3.0 Electrical Specifications (Continued) 8.3.4 ACCESS.bus Interface The following tables describes the timing for all ACCESS.bus signals. Notes: 1) All ACCESS.bus timing is not 100% tested. 2) In this table tCLK =1/24 MHz =41.7 ns. Table 8-15. ACCESS.bus Input Timing Parameters Symbol Parameter Min Max Unit Comments tBUFi Bus free time between Stop and Start condition tSCLhigho tCSTOsi AB1C/AB2C setup time 8 * tCLK -tSCLri Before Stop condition tCSTRhi AB1C/AB2C hold time 8 * tCLK -tSCLri After Start condition tCSTRsi AB1C/AB2C setup time 8 * tCLK -tSCLri Before Start condition tDHCsi Data high setup time 2 * tCLK Before AB1C/AB2C rising edge tDLCsi Data low setup time 2 * tCLK Before AB1C/AB2C rising edge tSCLfi AB1D/AB2D fall time 300 ns tSCLri AB1D/AB2D rise time 1 µs tSCLlowi AB1C/AB2C low time 16 * tCLK After AB1C/AB2C falling edge tSCLhighi AB1C/AB2C high time 16 * tCLK After AB1C/AB2C rising edge tSDAfi AB1D/AB2D fall time 300 ns tSDAri AB1D/AB2D rise time 1 µs tSDAhi AB1D/AB2D hold time 0 After AB1C/AB2C falling edge tSDAsi AB1D/AB2D setup time 2 * tCLK Before AB1C/AB2C rising edge Table 8-16. ACCESS.bus Output Timing Parameters Symbol Parameter Min Max Unit Comments tSCLhigho AB1C/AB2C high time K * tCLK -1 µs After AB1C/AB2C rising edge1 tSCLlowo AB1C/AB2C low time K * tCLK -1 µs After AB1C/AB2C falling edge tBUFo Bus free time between Stop and Start condition tSCLhigho 2 1 µs tCSTOso AB1C/AB2C setup time tSCLhigho 2 1 µs Before Stop condition tCSTRho AB1C/AB2C hold time tSCLhigho 2 1 µs After Start condition tCSTRso AB1C/AB2C setup time tSCLhigho 2 1 µs Before Start condition tDHCso Data high setup time tSCLhigho 2 -tSDAro 1 µs Before AB1C/AB2C rising edge tDLCso Data low setup time tSCLhigho 2 -tSDAfo 1 µs Before AB1C/AB2C rising edge tSCLfo AB1D/AB2D signal fall time 300 ns tSCLro AB1D/AB2D signal rise time 1 µs |
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