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PC87363 Datasheet(PDF) 27 Page - National Semiconductor (TI) |
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PC87363 Datasheet(HTML) 27 Page - National Semiconductor (TI) |
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27 / 200 page  1.0 Signal/Pin Connection and Description (Continued) 27 www.national.com 1.4.15 Strap Configuration 1.4.16 System Wake-Up Control RTS1 RTS2 98 106 O O3/6 VDD Request to Send. When low, indicate to the modem or other data transfer device that the corresponding UART is ready to exchange data. A system reset sets these signals to inactive high, and loopback operation holds them inactive. RTS1 is used also as TEST. SIN1 SIN2 97 105 I INTS VDD Serial Input. Receive composite serial data from the communications link (peripheral device, modem or other data transfer device). SOUT1 SOUT2 99 107 O O3/6 VDD Serial Output. Send composite serial data to the communications link (peripheral device, modem or other data transfer device). These signals are set active high after a system reset. Signal Pin/s I/O Buffer Type Power Well Description BADDR 101 I INSTRP VDD Base Address. Sampled by the trailing edge of the system reset to determine the base address of the configuration Index-Data register pair. During reset, it is pulled down by internal 30Kohm resistor. If no pull-up resistor is connected, it is sampled low, setting the Index-Data pair at 2Eh-2Fh. Connecting a 10K external pull-up resistor to VDD would make it sample high, setting the Index-Data pair at 4Eh-4Fh. PSLDC0 PSLDC1 99 107 I INSTRP VSB Note 1. Note 1.Make sure that the Serial Port driver is back-drive protected. Power Supply and LED Configuration. If no pull-up resistor is connected to these pins, pins 33-35 and 37 function as PWBTOUT, PSON, PWBTIN and SLPS5 respectively. Connecting a 10K external pull-up resistor to VSB causes these pins to function as GPOS0, GPOS1, GPIS2, respectively. PSONPOL 109 I INSTRP VSB Note 1. Power Supply On Polarity. If no pull-up resistor is connected to this pin, PSON is set active low with open-drain output. Connecting a 10K external pull-up resistor to VSB causes PSON to be set to active high with push-pull output. TEST 98 I INSTRP VDD Test. If sampled high on the trailing edge of system reset, this signal forces the device into test mode. This pin is for National Semiconductor use only, and should be left unconnected. Signal Pin/s I/O Buffer Type Power Well Description LED1 LED2 25 26 O O12/12 VSB LED. VSB-powered pins with programmable outputs, each of which can be used to produce a 0, 0.25, 0.5, 1, 4 Hz waveform for LED control. GPIE6-7 58-59 I INTS VSB General-Purpose Input Event GPIOE0-5 23-28 I/O INTS/ OD6,O3/6 VSB General-Purpose I/O Event. VSB-powered pins. GPIS2-3 35-36 I INTS VSB General-Purpose Input Standby. VSB-powered pins. GPOS0-1 33-34 O OD6,O3/6 VSB General-Purpose Output Standby. VSB-powered pins. Signal Pin/s I/O Buffer Type Power Well Description |
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