PC87570 datasheet(32/168 Pages) NSC

32 / 168 page

Signal/Pin Connection and Description

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2.8.2

Accessing External Memory

External Memory Configuration is enabled whenever the

Base Memory Shadow is off (MCFG.SHOFF=1). The BIU

Zone 0 Configuration Register (SZCFG0) controls the

memory access parameters.

The interface to the External Memory is executed using the

SEL0, RD, WR0-1, A0-18 and D0-15 signals. Not all the sig-

nals are used in every configuration. Table 2-7 summarizes

the MCFG bit settings, and the signals used for the memory

interface in each configuration.

Figure 2-4 shows the External Memory Address Range

mapping to the CR16A core.

External Memory Mapping into Shared BIOS Memory

When the shared BIOS memory is enabled (SHBM=0), the

External memory address range is mapped into a memory

device with larger address space. This External Memory ac-

cess is mapped by padding the core’s 16 lower address bits

with fixed values from the Page Register (used as most sig-

nificant address lines). See Table 2-8 for details on how to

configure various elements for External Memory expansion.

56 K

64 K

128 K

256 K

192 K

Address Map

PC87570

2 K

On-Chip Base Memory

MCFG.SHOFF=0

MCFG.SHOFF=1

Figure 2-2. On-Chip Base Memory (Zone 1) Address Range

56 K

64 K

128 K

256 K

192 K

Off-Chip Base Memory

Address Map

Off-Chip Base Memory

128 K

PC87570

MCFG.SHOFF=0

MCFG.SHOFF=1

Figure 2-3. Off-Chip Base Memory (Zone 1) Address Range

56 K

PC87570 Datasheet(PDF) 32 Page - National Semiconductor (TI)

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