PC87570 datasheet(4/168 Pages) NSC

4 / 168 page

Table of Contents

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Table of Contents

Highlights....................................................................................................................................................... 1

1.0

Introduction

1.1

INTERNAL ARCHITECTURE .................................................................................................... 14

1.1.1

Processing Unit ........................................................................................................... 14

1.1.2

BIU ............................................................................................................................... 14

1.1.3

Memory ........................................................................................................................ 14

1.1.4

HBI ............................................................................................................................... 14

1.1.5

Peripherals .................................................................................................................. 14

1.2

EXPANSION OPTIONS ............................................................................................................. 15

1.3

OPERATING ENVIRONMENTS ................................................................................................ 15

1.3.1

IRE Environment ......................................................................................................... 16

1.3.2

IRD Environment ......................................................................................................... 17

1.3.3

DEV Environment ........................................................................................................ 18

2.0

Signal/Pin Connection and Description

2.1

CONNECTION DIAGRAMS ...................................................................................................... 19

2.2

SIGNAL/PIN DESCRIPTIONS ................................................................................................... 21

2.3

RESET SOURCES AND TYPES ............................................................................................... 26

2.3.1

Power-Up Reset .......................................................................................................... 26

2.3.2

Warm Reset .................................................................................................................26

2.3.3

WATCHDOG Reset ..................................................................................................... 26

2.3.4

Triggering Reset .......................................................................................................... 26

2.4

STRAP PINS ............................................................................................................................ 26

2.4.1

Setting the Environment .............................................................................................. 26

2.4.2

Other Strap Pin Settings .............................................................................................. 26

2.4.3

System Load on Strap Pins ......................................................................................... 27

2.4.4

Strap Inputs During Idle Mode ..................................................................................... 27

2.4.5

Strap Pin Status Register (STRPST) ........................................................................... 27

2.5

ALTERNATE FUNCTIONS ........................................................................................................ 27

2.6

SYSTEM CONFIGURATION REGISTERS ............................................................................... 29

2.6.1

Module Configuration Register (MCFG) ...................................................................... 29

2.6.2

PAGE Register ............................................................................................................ 30

2.7

SHARED MEMORY CONFIGURATION ................................................................................... 30

2.8

MEMORY MAP .......................................................................................................................... 30

2.8.1

Accessing Base Memory ............................................................................................. 31

2.8.2

Accessing External Memory ........................................................................................ 32

2.8.3

Accessing I/O Expansion Space ................................................................................. 33

3.0

Bus Interface Unit (BIU)

3.1

FEATURES ................................................................................................................................ 34

3.2

FUNCTIONAL DESCRIPTION .................................................................................................. 34

3.2.1

Interfacing .................................................................................................................... 34

3.2.2

Static Memory and I/O Support ................................................................................... 34

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