PC87570 datasheet(33/168 Pages) NSC

33 / 168 page

Signal/Pin Connection and Description

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Table 2-7. External Memory Conﬁguration Settings

Table 2-8. External Memory Address Expansion Scheme

1. Legend:

X - Alternate function used (I/O port)

Ai - Signal outputs address bit i when the External Memory accessed

Page - Signal outputs the page deﬁned in the Page Register.

2.8.3

Accessing I/O Expansion Space

The I/O expansion protocol permits you to implement I/O

ports in the system, besides those available on-chip, in all

three environments (IRD, IRE and Dev). In IRD and Dev en-

vironments, the I/O expansion protocol enables you to im-

plement the functionality of I/O ports PF, PG and PH using

off-chip external logic. Access to these ports is through the

addresses defined in Chapter A on page 156. The I/O ex-

pansion space is mapped to the address space FB00-

FBFFh. You can use the I/O expansion space as follows:

Addresses in the range FB00h-FB11h may be used to

restore GPIO ports PF, PG and PH.

Address FBFEh is used only in Dev environment by

the MCFGSH Register, and must be written after each

write to the MCFG with the same data written to the

MCFG.

Addresses in the range FB30h-FB5Fh are reserved for

development board use.

The protocol accesses the off-chip I/O expansion using I/O

zone of the BIU. The zone select signal (SELIO), address

lines A0-7 and the RD and WR0 signals, are used to inter-

face to the off-chip logic.

External

Memory

Conﬁguration

MCFG

SZCFG0.BW

Interface Signals

SHOFF

A15E

EXM16

Control

Data

Addr

Disabled

32K x8

SEL0,

WR0, RD

D0-7

A0-14

64K x8

A0-15

32K x16

SEL0,

WR0-1, RD

D0-15

A0-14

64K x16

A0-15

SHBM

PEALT.1

MCFG.A15E

A181

A17

A16

A15

Page17

Page16

A15

Page18

56 K

64 K

128 K

256 K

192 K

Address Map

External Memory Address

PC87570

32 K

MCFG.A15E=0

MCFG.A15E=1

56 K

Figure 2-4. External Memory (Zone 0) Address Range

PC87570 Datasheet(PDF) 33 Page - National Semiconductor (TI)

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