PC87570 datasheet(94/168 Pages) NSC

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PS/2 Interface

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When a start bit is detected, data transmission begins by

outputting bit-0 (LSB) of the transmitted data and setting the

data bits WDAT1, WDAT2 and WDAT3 in the PSOSIG reg-

ister. This allows bit-0 of the transmitted data to be output

on the PS/2 data signal (PSDAT1, PSDAT2 or PSDAT3, ac-

cording to the active channel).

Hardware setting (1) the SOT bit and storing the active

channel number in the ACH field, indicates transmission of

the start bit in the PSTAT register. In addition, if PSIEN.SO-

TIE is set, then an interrupt signal to the ICU is set high. The

firmware may use this interrupt to start a time-out timer for

the data transfer.

Transmit Active

After identifying the start bit, the shift mechanism enters the

Transmit-Active state. The clock signal of the selected de-

vice (PSCLK1, PSCLK2 or PSCLK3) sets the data bit rate.

After each of the next seven falling edges of the clock line,

one more data bit (bits 1 through 7) is driven on the data line

of the active channel (either PSDAT1, PSDAT2 or

PSDAT3).

On the ninth falling edge of the clock, the parity bit is output.

The parity bit is high (1) if the number of bits with a value of

1 in the transmitted data was even (i.e., odd parity).

The tenth falling edge causes a ‘1’ to be output as a stop bit.

The data signal remains high to allow the PS/2 device to

send the line control bit.

The auxiliary device then completes the transfer by sending

the line-control bit. The line-control bit, is identified by the

data signal being low after the 11th falling edge of the clock.

End of Transmission

The End-Of-Transmission state is entered by detecting the

line-control bit. In response, the shift mechanism holds all

clock signals low and all data signals are pulled-high by the

internal pull-up if enabled.

The End-Of-Transaction flag (PSTAT.EOT) is set to indi-

cate that the transmit operation was completed, and, if the

PSIEN.EOTIE bit is set, then the interrupt signal to the ICU

is set high.

The shift mechanism stays at this state until being reset.

Figure 12-6 illustrates the transmit byte sequence as it is

defined by the PS/2 standard.

Transfer Abort

At each stage of a receive or transmit operation, the trans-

action can be aborted by clearing all three channel enable

bits (CLK1-3) in the PS/2 Output Signal Register (PSOSIG)

to 0. This resets the shifter state machine and puts it in the

“enabled-inactive” state. If the shift mechanism is in Trans-

mit Inactive or Transmit Idle states, the WDAT1, WDAT2

and WDAT3 bits should also be set.

12.4 SHIFT MECHANISM DISABLED

The shift mechanism is disabled when PSCON.EN is

cleared (0). In this state, the PS/2 clock and data signals are

controlled by the firmware, which performs the PS/2 proto-

col by manipulating the PS/2 clock and data signals.

12.4.1

Clock Signal Control

The CLK1, CLK2 and CLK3 bits in the PSOSIG register

control the value of the respective clock signals (PSCLK1,

PSCLK2 and PSCLK3). When cleared (0), the pin is held

low. When set (1), the open drain output is open and the re-

spective clock signal is either floating or held high by the

pull-up. In this case, an external device may force the re-

spective clock signal low.

When reading the PSISIG register, bits RCLK1, RCLK2 and

RCLK3 indicate the current state of the corresponding clock

signal.

12.4.2

Data Signal Control

The WDAT1, WDAT2 and WDAT3 bits in PSOSIG register

control the value of the respective data signals (PSDAT1,

PSDAT2 and PSDAT3). When cleared (0), the respective

data signal is held low. When set, the open drain output is

open and the respective data signal is held high by the pull-

up. In this case, if PSCON.WPUEN is set (1), an external

device may force the respective data signal low.

When reading the PSISIG, register bits RDAT1, RDAT2

and RDAT3 indicate the current state of the corresponding

data signal.

12.4.3

Interrupt Generation

When PSIEN.DSMIE bit is set (1), the clock input signals

are connected to the Interrupt Control Unit (ICU) for an in-

terrupt driven PS/2 protocol. The three interrupts that are

generated are PSINT1, PSINT2 and PSINT3 for channels

1, 2 and 3, respectively.

CLK

DATA

Bit 0

Parity Bit

Stop Bit

Start Bit

1st

CLK

2nd

CLK

9th

CLK

11th

CLK

I/O

Inhibit

10th

CLK

Figure 12-6. PS/2 Transmit Data Byte Timing

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