PC87570 datasheet(101/168 Pages) NSC

101 / 168 page

ACCESS.bus (ACB) Interface

101

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Master Transmit

After becoming the bus master, the device can start trans-

mitting data on the ACCESS.bus.

To transmit a byte the software should:

1. Check that the ACBST.BER and ACBST.NEGACK bits

are cleared and ACBST.SDAST is set. Also, if

ACBCTL1.STASTRE is set, check that ACBST.STAS-

TR is cleared (and clear it if required).

2. Write the data byte to be transmitted to the ACBSDA

When the slave responds with a negative acknowledge, the

ACBST.NEGACK bit is set and the ACBST.SDAST bit re-

mains cleared. In this case, if ACBCTL1.INTEN is set, an in-

terrupt is sent to the core.

Master Receive

After becoming the bus master, the device can start receiv-

ing data on the ACCESS.bus.

To receive a byte the software should:

Check that ACBST.SDAST is set and ACBST.BER is

cleared. Also, if ACBCTL1.STASTRE is set, check that

ACBST.STASTR is cleared (and clear it if required).

Set the ACBCTL1.ACK bit to 1, if the next byte is the

last byte that should be read. This causes a negative

acknowledge to be sent.

Read the data byte from the ACBSDA register.

Master Stop

To end a transaction set (1) ACBCTL1.STOP, before clear-

ing

the

current

stall

flag

(i.e.,

ACBST.SDAST,

ACBST.NEGACK or ACBST.STASTR). This causes the

module to send a Stop Condition immediately, and clear

ACBCTL1.STOP. A Stop Condition may be issued only

when the PC87570 is the active bus master (ACBST.MAS-

TRER=1).

Master Bus Stall

The ACB module can stall the ACCESS.bus between trans-

fers while waiting for the core’s response. The AC-

CESS.bus is stalled by holding the SCL signal low after the

acknowledge cycle. Note that this is interpreted as the be-

ginning of the following bus operation. The user must make

sure that the next operation is prepared before the flag that

causes the bus stall is cleared.

The flags that can cause a bus stall in Master mode are:

Negative acknowledge after sending a byte

(ACBSTNEGACK=1).

ACBST.SDAST bit is set.

ACBCTL1.STASTRE=1, after a successful start (ACB-

ST.STASTR=1).

Repeated Start

A repeated start is performed when the PC87570 is already

the bus master (ACBST.MASTER is set). In this case the

ACCESS.bus is stalled and the ACB module is awaiting the

core

handling

due

to:

negative

acknowledge

(ACBST.NEGACK=1), empty buffer (ACBST.SDAST=1)

and/or a stall after start (ACBST.STASTR=1).

For a Repeated Start:

Set (1) ACBCTL1.START.

In Master Receive mode, read the last data item from

ACBSDA.

Follow the address send sequence, as described in

“Sending the Address Byte” on page 100.

If the ACB was awaiting handling due to ACBST.STAS-

TR=1, clear it only after writing the requested address

and direction to ACBSDA.

Master Error Detection

The ACB detects illegal Start or Stop Conditions (i.e., a

Start or Stop Condition within the data transfer, or the ac-

knowledge cycle) and a conflict on the data lines of the AC-

CESS.bus. If an illegal condition is detected, BER is set,

and the Master mode is exited (ACBSTMASTER is

cleared).

Bus Idle Error Recovery

When a request to become the active bus master or a re-

start operation fails, the ACBST.BER bit is set to indicate

the error. In some cases, both the PC87570 and the other

device may identify the failure and leave the bus idle. In this

case, the start sequence may be uncompleted and the AC-

CESS.bus may remain deadlocked forever.

To recover from deadlock, use the following sequence:

Clear ACBST.BER bit and the ACBCST.BB bit.

Wait for a time-out period to check that there is no oth-

er active master on the bus (i.e., ACBCST.BB remains

cleared).

Disable, and re-enable the ACB to put it in the non-ad-

dressed slave mode. (This completely resets the mod-

ule).

At this point some of the slaves may not identify the bus er-

ror. To recover, the ACB module becomes the bus master:

it asserts a Start Condition, sends an address byte, then as-

serts a Stop Condition which synchronizes all the slaves.

13.3.2

Slave Mode

A slave device waits in Idle mode for a master to initiate a

bus transaction. Whenever the ACB module is enabled, and

it is not acting as a master (i.e., ACBST.MASTER is

cleared), it acts as a slave device.

Once a Start Condition on the bus is detected, the PC87570

checks whether the address sent by the current master

matches either:

The ACBADDR.ADDR value if ACBADDR.SAEN=1, or

The general call address if ACBCTL1.GCMEM=1.

This match is checked even when ACBST.MASTER is set.

If a bus conflict (on SDA or SCL) is detected, ACBST.BER

is set, ACBST.MASTER is cleared and the PC87570 con-

tinues to search the received message for a match.

PC87570 Datasheet(PDF) 101 Page - National Semiconductor (TI)

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