ST7LITEUS5 datasheet(113/136 Pages) STMICROELECTRONICS

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Electrical characteristics

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Figure 59.

Typical VOL vs. VDD (HS pins)

Figure 60.

Typical VDD-VOH vs. VDD (HS pins)

12.9

Control pin characteristics

The reset network protects the device against parasitic resets.

The output of the external reset circuit must have an open-drain output to drive the ST7

reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset

(LVD or watchdog).

Whatever the reset source is (internal or external), the user must ensure that the level on the

RESET pin can go below the VIL max. level specified in Table 65. Otherwise the reset will

not be taken into account internally.

Because the reset circuit is designed to allow the internal reset to be output in the RESET

pin, the user must ensure that the current sunk on the RESET pin is less than the absolute

maximum value specified for IINJ(RESET) in Table 44.

Refer to Figure 61 and Figure 62 for a description of the RESET pin protection circuit with

LVD enabled and disabled.

100

2.4

2.6 2.8

3.2

3.4 3.6

3.8

4.2 4.4

4.6

4.8

5.2

5.4

5.6 5.8

Vdd [V]

-45°C

25°C

90°C

130°C

100

150

200

250

300

350

400

450

500

2.4

2.6

2.8

3.2

3.4

3.6

3.8

4.2

4.4

4.6

4.8

5.2

5.4

5.6

5.8

Vdd [V]

-45°C

25°C

90°C

130°C

200

300

400

500

600

700

800

900

2.4

2.6 2.8

3.2

3.4

3.6 3.8

4.2

4.4

4.6 4.8

5.2

5.4

5.6 5.8

Vdd [V]

-45°C

25°C

90°C

130°C

100

120

140

160

180

200

2.4 2.6

2.8

3.2 3.4

3.6 3.8

4.2 4.4

4.6 4.8

5.2

5.4 5.6

5.8

Vdd [V]

-45°C

25°C

90°C

130°C

100

200

300

400

500

600

700

2.4

2.6

2.8

3.2

3.4

3.6

3.8

4.2

4.4

4.6

4.8

5.2

5.4

5.6

5.8

Vdd [V]

-45°C

25°C

90°C

130°C

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